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? 2005 integrated device technology, inc. dsc-6969/- idt and the idt logo are trademarks of integrated device technology, inc. 1 september 2005 octal t1/e1 short haul line interface unit with single ended option IDT82V2048S functional block diagram figure-1 block diagram jitter attenuator jitter attenuator b8zs/ hdb3/ami decoder b8zs/ hdb3/ami encoder remote loopback analog loopback slicer peak detector clk&data recovery (dpll) line driver waveform shaper iblc detector los detector iblc generator digital loopback ais detector one of eight identical channels register file control interface clock generator mode[2:0] cs /jas ts2/sclk/ale/ as ts1/ rd /r/ w ts0/sdi/ wr / ds sdo/rdy/ ack int lp[7:0]/d[7:0]/ad[7:0] mc[3:0]/a[4:0] mclk trst tck tms tdi tdo jtag tap rtipn rringn ttipn tringn vddio vddt vddd vdda losn rclkn rdn/rdpn cvn/rdnn tclkn bpvin/tdnn tdn/tdpn g.772 monitor transmit all ones oe clke features ! fully integrated octal t1/e1 short haul line interface which supports 100 ? t1 twisted pair, 120 ? e1 twisted pair and 75 ? e1 coaxial applications ! optional single ended recei ve termination liu on rtipn/ rringn for 75 ? e1 coaxial applications ! selectable single rail mode or dual rail mode and ami or b8zs/hdb3 encoder/decoder ! built-in transmit pre-equaliz ation meets g.703 & t1.102 ! selectable transmit/receive jitte r attenuator meets etsi ctr12/ 13, itu g.736, g.742, g.823 and at&t pub 62411 specifications ! sonet/sdh optimized jitter attenuator meets itu g.783 mapping jitter specification ! digital/analog los detector meets itu g.775, ets 300 233 and t1.231 ! itu g.772 non-intrusive monitoring for in-service testing for any one of channel 1 to channel 7 ! low impedance transmit drivers with high-z ! selectable hardware and parallel/serial host interface ! local, remote and inband loopback test functions ! hitless protection switching (hps) for 1 to 1 protection without relays ! jtag boundary scan for board test ! 3.3 v supply with 5 v tolerant i/o ! low power consumption ! operating temperat ure range: -40 c to +85 c ! available in 144-pin thin quad flat pack (tqfp) and 160-pin plastic ball grid array (pbga) packages
2 IDT82V2048S octal t1/e1 short haul liu with sing le ended option industrial temperature ranges description the IDT82V2048S is a single chip, 8-channel t1/e1 short haul pcm transceiver with a reference clock of 1.544 mhz (t1) or 2.048 mhz (e1). the IDT82V2048S contains 8 transmitters and 8 receivers. all the receivers and transmitters can be programmed to work either in single rail mode or dual ra il mode. b8zs/hdb3 or ami encoder/ decoder is selectable in single ra il mode. pre-encoded transmit data in nrz format can be accepted when the device is configured in dual rail mode. the receivers perform clock and data recovery by using inte- grated digital phase-locked loop. as an option, the raw sliced data (no retiming) can be output on the receiv e data pins. transmit equalization is implemented with low-impedance out put drivers that provide shaped waveforms to the transformer, guaranteeing template conformance. a jitter attenuator is integrated in the IDT82V2048S and can be switched into either the transmit path or the receive path for all channels. the jitter attenuation performance meets etsi ctr12/13, itu g.736, g.742, g.823, and at&t pub 62411 specifications. the IDT82V2048S offers hardware control mode and software control mode. software control mode wo rks with either serial host inter- face or parallel host interface. the latter works via an intel/motorola compatible 8-bit parallel interface for both multiplexed or non-multi- plexed applications. hardware cont rol mode uses multiplexed pins to select different operation modes when the host interface is not available to the device. the IDT82V2048S also provid es loopback and jtag boundary scan testing functions. using the integrated monitoring function, the IDT82V2048S can be configured as a 7-channel transceiver with non- intrusive protected monitoring points. the IDT82V2048S can be used for sdh/sonet multiplexers, central office or pbx, digital acce ss cross connects, digital radio base stations, remote wireless modul es and microwave transmission systems. pin configurations figure-2 tqfp144 package pin assignment IDT82V2048S (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 td7/tdp7 tclk7 los6 cv6/rdn6 rd6/rdp6 rclk6 bpvi6/tdn6 td6/tdp6 tclk6 mclk mode2 a4 mc3/a3 mc2/a2 mc1/a1 mc0/a0 vddio gndio vddd gndd lp0/d0/ad0 lp1/d1/ad1 lp2/d2/ad2 lp3/d3/ad3 lp4/d4/ad4 lp5/d5/ad5 lp6/d6/ad6 lp7/d7/ad7 tclk1 td1/tdp1 bpvi1/tdn1 rclk1 rd1/rdp1 cv1/rdn1 los1 tclk0 bpvi3/tdn3 rclk3 rd3/rdp3 cv3/rdn3 los3 rtip3 rring3 vddt3 ttip3 tring3 gndt3 rring2 rtip2 gndt2 tring2 ttip2 vddt2 rtip1 rring1 vddt1 ttip1 tring1 gndt1 rring0 rtip0 gndt0 tring0 ttip0 vddt0 mode1 los0 cv0/rdn0 rd0/rdp0 rclk0 bpvi0/tdn0 td0/tdp0 td4/tdp4 tclk4 los5 cv5/rdn5 rd5/rdp5 rclk5 bpvi5/tdn5 td5/tdp5 tclk5 tdi tdo tck tms trst ic ic vddio gndio vdda gnda mode0/code cs /jas ts2/sclk/ale/ as ts1/ rd /r/ w ts0/sdi/ wr / ds sdo/rdy/ ack int tclk2 td2/tdp2 bpvi2/tdn2 rclk2 rd2/rdp2 cv2/rdn2 los2 tclk3 td3/tdp3 bpvi4/tdn4 rclk4 rd4/rdp4 cv4/rdn4 los4 oe clke vddt4 ttip4 tring4 gndt4 rtip4 rring4 gndt5 tring5 ttip5 vddt5 rring5 rtip5 vddt6 ttip6 tring6 gndt6 rtip6 rring6 gndt7 tring7 ttip7 vddt7 rring7 rtip7 los7 cv7/rdn7 rd7/rdp7 rclk7 bpvi7/tdn7
3 IDT82V2048S octal t1/e1 short haul liu with sing le ended option industrial temperature ranges figure-3 pbga160 package pin assignment vddt 4 tring 4 gndt 4 rtip 4 rtip 7 gndt 7 tring 7 vddt 7 rdn 7 rclk 4 rdp 4 rdn 4 rdp 7 rclk 7 vddt 5 tring 5 gndt 5 rtip 5 rtip 6 gndt 6 vddt 6 rdn 6 rclk 5 rdp 5 rdn 5 rdp 6 rclk 6 vddt 5 ttip 5 gndt 5 rring 5 rring 6 gndt 6 ttip 6 vddt 6 tdn 6 tclk 5 tdp 5 tdn 5 tdp 6 tclk 6 los 4 los 7 los 6 oe clke los 5 mode 2 mclk tms a4 mc 3 tck tdo tdi mc 2 mc 1 gndio gndio mc 0 vddio ic trst lp 0 vddio gnda gndd lp 1 vdda ic mode 0 lp 2 vddd cs lp 3 lp 4 ts 0 ts 1 ts 2 lp 5 lp 6 los 3 los 0 los 1 sdo int los 2 mode 1 lp 7 vddt 2 ttip 2 gndt 2 rring 2 rring 1 gndt 1 ttip 1 vddt 1 tdn 1 tclk 2 tdp 2 tdn 2 tdp 1 tclk 1 vddt 2 tring 2 gndt 2 rtip 2 rtip 1 gndt 1 tring 1 vddt 1 rdn 1 rclk 2 rdp 2 rdn 2 rdp 1 rclk 1 vddt 3 ttip 3 gndt 3 rring 0 gndt 0 ttip 0 vddt 0 tdn 0 tclk 3 tdp 3 tdn 3 tdp 0 tclk 0 vddt 3 tring 3 gndt 3 rtip 3 rtip 0 gndt 0 tring 0 vddt 0 rdn 0 rclk 3 rdp 3 rdn 3 rdp 0 rclk 0 vddt 7 ttip 7 gndt 7 rring 7 rring 4 gndt 4 ttip 4 vddt 4 tdn 4 tclk 7 tdp 7 tdn 7 tdp 4 tclk 4 tring 6 IDT82V2048S (bottom view) rring 3 a b c d e f g h j k l m n p a b c d e f g h j k l m n p 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 3 4 5 6 7 8 9 10 11 12 13 14
4 IDT82V2048S octal t1/e1 short haul liu with single ended industrial temperature ranges 1 pin description table-1 pin description name type pin no. description tqfp144 pbga160 transmit and receive line interface ttip0 ttip1 ttip2 ttip3 ttip4 ttip5 ttip6 ttip7 tring0 tring1 tring2 tring3 tring4 tring5 tring6 tring7 analog output 45 52 57 64 117 124 129 136 46 51 58 63 118 123 130 135 n5 l5 l10 n10 b10 d10 d5 b5 p5 m5 m10 p10 a10 c10 c5 a5 ttipn/tringn: transmit bipolar tip/ring for channel 0~7 these pins are the differential line driver outputs. they will be in high-z if pin oe is low or the correspond- ing pin tclkn is low (pin oe is global control, while pin tclkn is per-channel control). in host mode, each pin can be in high-z by programming a ?1? to the corresponding bit in register oe (1) . rtip0 rtip1 rtip2 rtip3 rtip4 rtip5 rtip6 rtip7 rring0 rring1 rring2 rring3 rring4 rring5 rring6 rring7 analog input 48 55 60 67 120 127 132 139 49 54 61 66 121 126 133 138 p7 m7 m8 p8 a8 c8 c7 a7 n7 l7 l8 n8 b8 d8 d7 b7 differential line receiver inputs: rtipn/rringn rtipn/rringn: receive bipolar tip/ring for channel 0~7 these pins are the differential rtipn/rringn liu inputs for 100 ? t1 twisted pair, 120 ? e1 twisted pair and 75 ? e1 coaxial applications. single ended line receiver inputs: rtipn rtipn: receive single ended input for channel 0~7 these pins are the single ended receive inputs for 75 ? e1 coaxial applications. for more information about single ended receive termination, refer to 2.4.1 single ended receive termi- nation . 1 . register name is indicated by bo ld capital letter. for example, oe indicates output enable register.
5 IDT82V2048S octal t1/e1 short haul liu with single ended industrial temperature ranges transmit and receive digital data interface td0/tdp0 td1/tdp1 td2/tdp2 td3/tdp3 td4/tdp4 td5/tdp5 td6/tdp6 td7/tdp7 bpvi0/tdn0 bpvi1/tdn1 bpvi2/tdn2 bpvi3/tdn3 bpvi4/tdn4 bpvi5/tdn5 bpvi6/tdn6 bpvi7/tdn7 i 37 30 80 73 108 101 8 1 38 31 79 72 109 102 7 144 n2 l2 l13 n13 b13 d13 d2 b2 n3 l3 l12 n12 b12 d12 d3 b3 tdn: transmit data for channel 0~7 when the device is in single rail mode, the nrz data to be transmitted is input on this pin. data on tdn is sampled into the device on the falling edges of tclkn, and encoded by ami or b8zs/hdb3 line code rules before being transmitted to the line. bpvin: bipolar violation insertion for channel 0~7 bipolar violation insertion is available in single rail mode 2 ( see table-2 on page 14 and table-3 on page 14 ) with ami enabled. a low-to-high transition on this pin will make the next logic one to be transmitted on tdn the same polarity as the previous pulse, and violate the ami rule. this is for testing. tdpn/tdnn: positive/negative transmit data for channel 0~7 when the device is in dual rail mode, the nrz data to be transmitted for positive/negative pulse is input on this pin. data on tdpn/tdnn are sampled on the falling edges of tclkn. the line code in dual rail mode is as the follow: pulling pin tdnn high for more than 16 consecutive tclk clock cycles will configure the corresponding channel into single rail mode 1 (see table-2 on page 14 and table-3 on page 14 ). tclk0 tclk1 tclk2 tclk3 tclk4 tclk5 tclk6 tclk7 i 36 29 81 74 107 100 9 2 n1 l1 l14 n14 b14 d14 d1 b1 tclkn: transmit clock for channel 0~7 the clock of 1.544 mhz (for t1 mode) or 2.048 mhz (for e1 mode) for transmit is input on this pin. the transmit data at tdn/tdpn or tdnn is sampled into the device on the falling edges of tclkn. pulling tclkn high for more than 16 mclk cycles, the corresponding transmitter is set in transmit all ones (taos) state (when mclk is clocked). in ta os state, the taos generator adopts mclk as the clock reference. if tclkn is low, the corresponding transmit channel is set into power down state, while driver output ports become high-z. different combinations of tclkn and mclk result in different transmit mode. it is summarized as the fol- lows: table-1 pin description (continued) name type pin no. description tqfp144 pbga160 tdpn tdnn output pulse 0 0 space 0 1 negative pulse 1 0 positive pulse 1 1 space mclk tclkn transmit mode clocked clocked normal operation clocked high ( 16 mclk) transmit all ones (taos) signals to the line side in the corresponding transmit channel. clocked low ( 64 mclk) the corresponding transmit channel is set into power down state. high/low tclk1 is clocked tclkn is clocked normal operation tclkn is high ( 16 tclk1) transmit all ones (taos) signals to the line side in the corresponding transmit channel. tclkn is low ( 64 tclk1) corresponding transmit channel is set into power down state. the receive path is not affected by the status of tclk1. when mclk is high, all receive paths just slice the incoming data stream. when mclk is low, all the receive paths are powered down. high/low tclk1 is unavail- able. all eight transmitters (ttipn & tringn) will be in high-z.
6 IDT82V2048S octal t1/e1 short haul liu with single ended industrial temperature ranges rd0/rdp0 rd1/rdp1 rd2/rdp2 rd3/rdp3 rd4/rdp4 rd5/rdp5 rd6/rdp6 rd7/rdp7 cv0/rdn0 cv1/rdn1 cv2/rdn2 cv3/rdn3 cv4/rdn4 cv5/rdn5 cv6/rdn6 cv7/rdn7 o high-z 40 33 77 70 111 104 5 142 41 34 76 69 112 105 4 141 p2 m2 m13 p13 a13 c13 c2 a2 p3 m3 m12 p12 a12 c12 c3 a3 rdn: receive data for channel 0~7 in single rail mode, the received nrz data is output on this pin. the data is decoded by ami or b8zs/ hdb3 line code rule. cvn: code violation for channel 0~7 in single rail mode, the bipolar violation, code violation and excessive zeros will be reported by driving pin cvn high for a full clock cycle. however, only bipolar violation is indicated when ami decoder is selected. rdpn/rdnn: positive/negative receive data for channel 0~7 in dual rail mode with clock recovery, these pins ou tput the nrz data. a high signal on rdpn indicates the receipt of a positive pulse on rtipn/rringn while a high signal on rdnn indicates the receipt of a negative pulse on rtipn/rringn. the output data at rdn or rdpn/rdnn are clocked out on the falling edges of rclk when the clke input is low, or are clocked out on the rising edges of rclk when clke is high. in dual rail mode without clock recovery, these pins output the raw rz sliced data. in this data recovery mode, the active polarity of rdpn/rdnn is determi ned by pin clke. when pin clke is low, rdpn/rdnn is active low. when pin clke is high, rdpn/rdnn is active high. in hardware mode, rdn or rdpn/rdnn will remain active during los. in host mode, these pins will either remain active or insert alarm indication signal (ais) into the receive path, determined by bit aise in regis- ter gcf . rdn or rdpn/rdnn is set into high-z when the corresponding receiver is powered down. rclk0 rclk1 rclk2 rclk3 rclk4 rclk5 rclk6 rclk7 o high-z 39 32 78 71 110 103 6 143 p1 m1 m14 p14 a14 c14 c1 a1 rclkn: receive clock for channel 0~7 in clock recovery mode, this pin outputs the recovered clock from signal received on rtipn/rringn. the received data are clocked out of the device on the rising edges of rclkn if pin clke is high, or on falling edges of rclkn if pin clke is low. in data recovery mode, rclkn is the output of an internal exclusive or (xor) which is connected with rdpn and rdnn. the clock is recovered from the signal on rclkn. if receiver n is powered down, the corresponding rclkn is in high-z. mclk i 10 e1 mclk: master clock this is an independent, free running reference clock. a clock of 1.544 mhz (for t1 mode) or 2.048 mhz (for e1 mode) is supplied to this pin as the clock reference of the device for normal operation. in receive path, when mclk is high, the device slices the incoming bipolar line signal into rz pulse (data recovery mode). when mclk is low, all the receivers are powered down, and the output pins rclkn, rdpn and rdnn are switched to high-z. in transmit path, the operation mode is decided by the combination of mclk and tclkn (see tclkn pin description for details). note: wait state generation via rdy/ ack is not available if mclk is not provided. los0 los1 los2 los3 los4 los5 los6 los7 o 42 35 75 68 113 106 3 140 k4 k3 k12 k11 e11 e12 e3 e4 losn: loss of signal output for channel 0~7 a high level on this pin indicates the loss of signal when there is no transition over a specified period of time or no enough ones density in the received signal. the transition will return to low automatically when there is enough transitions over a specified period of time with a certain ones density in the received sig- nal. the los assertion and desertion criteria are described in 2.4.5 loss of signal (los) detection . table-1 pin description (continued) name type pin no. description tqfp144 pbga160
7 IDT82V2048S octal t1/e1 short haul liu with single ended industrial temperature ranges hardware/host control interface mode2 i (pulled to vddio/2) 11 e2 mode2: control mode select 2 the signal on this pin determines which control mode is selected to control the device: hardware control pins include mode[2:0], ts[2:0], lp[7:0], code, clke, jas and oe. serial host interface pins include cs , sclk, sdi, sdo and int . parallel host interface pins include cs , a[4:0], d[7:0], wr / ds , rd /r/ w , ale/ as , int and rdy/ ack . the device supports multiple parallel host interface as follows ( refer to mode1 and mode0 pin descriptions below for details ): mode1 i 43 k2 mode1: control mode select 1 in parallel host mode, the parallel interface operates with separate address bus and data bus when this pin is low, and operates with multiplexed address and data bus when this pin is high. in serial host mode or hardware mode, this pin should be grounded. mode0/code i 88 h12 mode0: control mode select 0 in parallel host mode, the parallel host interface is configured for motorola compatible hosts when this pin is low, or for intel compatible hosts when this pin is high. code: line code rule select in hardware control mode, the b8zs (for t1 mode)/hdb3 (for e1 mode) encoder/decoder is enabled when this pin is low, and ami encoder/decoder is enabled when this pin is high. the selections affect all the channels. in serial host mode, this pin should be grounded. cs /jas i (pulled to vddio/2) 87 j11 cs : chip select (active low) in host mode, this pin is asserted low by the host to enable host interface. a high to low transition must occur on this pin for each read/write operation and the level must not return to high until the operation is over. jas: jitter attenuator select in hardware control mode, this pin globally determines the jitter attenuator position: table-1 pin description (continued) name type pin no. description tqfp144 pbga160 mode2 control interface low hardware mode vddio/2 serial host interface high parallel host interface mode[2:0] host interface 100 non-multiplexed motorola mode interface 101 non-multiplexed intel mode interface 110 multiplexed motorola mode interface 111 multiplexed intel mode interface jas jitter attenuator (ja) configuration low ja in transmit path vddio/2 ja not used high ja in receive path
8 IDT82V2048S octal t1/e1 short haul liu with single ended industrial temperature ranges ts2/sclk/ ale/ as i86j12 ts2: template select 2 in hardware control mode, the signal on this pin is the most significant bit for the transmit template select. refer to 2.5.1 waveform shaper for details. sclk: shift clock in serial host mode, the signal on this pin is the shift clock for the serial interface. data on pin sdo is clocked out on falling edges of sclk if pin clke is high, or on rising edges of sclk if pin clke is low. data on pin sdi is always sampled on rising edges of sclk. ale: address latch enable in parallel intel multiplexed host mode, the address on ad[4:0] is sampled into the device on the falling edges of ale (signals on ad[7:5] are ignored). in non-multiplexed host mode, ale should be pulled high. as : address strobe (active low) in parallel motorola multiplexed host mode, the address on ad[4:0] is latched into the device on the falling edges of as (signals on ad[7:5] are ignored). in non-multiplexed host mode, as should be pulled high. ts1/ rd /r/ w i85j13 ts1: template select 1 in hardware control mode, the signal on this pin is the second most significant bit for the transmit template select. refer to 2.5.1 waveform shaper for details. rd : read strobe (active low) in parallel intel multiplexed or non-multiplexed host mode, this pin is active low for read operation. r/ w : read/write select in parallel motorola multiplexed or non-multiplexed host mode, the pin is active low for write operation and high for read operation. ts0/sdi/ wr / ds i84j14 ts0: template select 0 in hardware control mode, the signal on this pin is the least significant bit for the transmit template select. refer to 2.5.1 waveform shaper for details. sdi: serial data input in serial host mode, this pin input the data to the serial interface. data on this pin is sampled on the rising edges of sclk. wr : write strobe (active low) in parallel intel host mode, this pin is active low during write operation. the data on d[7:0] (in non-multi- plexed mode) or ad[7:0] (in multiplexed mode) is sampled into the device on the rising edges of wr . ds : data strobe (active low) in parallel motorola host mode, this pin is active low. during a write operation (r/ w = 0), the data on d[7:0] (in non-multiplexed mode) or ad[7:0] (in multiplexed mode) is sampled into the device on the rising edges of ds . during a read operation (r/ w = 1), the data is driven to d[7:0] (in non-multiplexed mode) or ad[7:0] (in multiplexed mode) by the device on the rising edges of ds . in parallel motorola non-multiplexed host mode, the address information on the 5 bits of address bus a[4:0] are latched into the device on the falling edges of ds . table-1 pin description (continued) name type pin no. description tqfp144 pbga160
9 IDT82V2048S octal t1/e1 short haul liu with single ended industrial temperature ranges sdo/rdy/ ack o83k14 sdo: serial data output in serial host mode, the data is output on this pin. in serial write operation, sdo is always in high-z. in serial read operation, sdo is in high-z only when sdi is in address/command byte. data on pin sdo is clocked out of the device on the falling edges of sclk if pin clke is high, or on the rising edges of sclk if pin clke is low. rdy: ready output in parallel intel host mode, the high level of this pin reports to the host that bus cycle can be completed, while low reports the host must insert wait states. ack : acknowledge out put (active low) in parallel motorola host mode, the low level of this pin indicates that valid information on the data bus is ready for a read operation or acknowledges the acceptance of the written data during a write operation. int o open drain 82 k13 int : interrupt (active low) this is an open drain, active low interrupt output. four sources may cause the interrupt. refer to 2.19 interrupt handling for details. lp7/d7/ad7 lp6/d6/ad6 lp5/d5/ad5 lp4/d4/ad4 lp3/d3/ad3 lp2/d2/ad2 lp1/d1/ad1 lp0/d0/ad0 i/o high-z 28 27 26 25 24 23 22 21 k1 j1 j2 j3 j4 h2 h3 g2 lpn: loopback select 7~0 in hardware control mode, pin lpn configures the corresponding channel in different loopback mode, as follows: refer to 2.17 loopback mode for details. dn: data bus 7~0 in non-multiplexed host mode, these pins are the bi-directional data bus. adn: address/data bus 7~0 in multiplexed host mode, these pins are the multiplexed bi-directional address/data bus. in serial host mode, these pins should be grounded. table-1 pin description (continued) name type pin no. description tqfp144 pbga160 lpn loopback configuration low remote loopback vddio/2 no loopback high analog loopback
10 IDT82V2048S octal t1/e1 short haul liu with single ended industrial temperature ranges a4 mc3/a3 mc2/a2 mc1/a1 mc0/a0 i 12 13 14 15 16 f4 f3 f2 f1 g3 mcn: performance monitor configuration 3~0 in hardware control mode, a4 must be connected to gnd. mc[3:0] are used to select one transmitter or receiver of channel 1 to 7 for non-intrusive monitoring. channel 0 is used as the monitoring channel. if a transmitter is monitored, signals on the corresponding pins ttipn and tringn are internally transmitted to rtip0 and rring0. if a receiver is monitored, signals on the corresponding pins rtipn and rringn are internally transmitted to rtip0 and rring0. the monitored is then output to rdp0 and rdn0 pins. in host mode operation, the signals monitored by channel 0 can be routed to ttip0/ring0 by activating the remote loopback in this channel. refer to 2.20 g.772 monitoring for more details. performance monitor configuration determined by mc[3:0] is shown below. note that if mc[2:0] = 000, the device is in normal operation of all the channels. an: address bus 4~0 when pin mode1 is low, the parallel host interface operates with separate address and data bus. in this mode, the signal on this pin is the address bus of the host interface. when pin mode1 is high or in serial host mode, these pins should be tied to gnd. oe i 114 e14 oe: output driver enable pulling this pin low can drive all driver output into high-z for redundancy application without external mechanical relays. in this condition, all other internal circuits remain active. clke i 115 e13 clke: clock edge select the signal on this pin determines the active edge of rclkn and sclk in clock recovery mode, or deter- mines the active level of rdpn and rdnn in the data recovery mode. see 2.3 clock edges on page 15 for details. jtag signals trst i pull-up 95 g12 trst : jtag test port reset (active low) this is the active low asynchronous reset to the jtag test port. this pin has an internal pull-up resistor and it can be left open. tms i pull-up 96 f11 tms: jtag test mode select the signal on this pin controls the jtag test performance and is clocked into the device on the rising edges of tck. this pin has an internal pull-up resistor and it can be left open. tck i 97 f14 tck: jtag test clock this pin input the clock of the jtag test. the data on tdi and tms are clocked into the device on the ris- ing edges of tck, while the data on tdo is clocked out of the device on the falling edges of tck. this pin should be connected to gndio or vddio pin when unused. table-1 pin description (continued) name type pin no. description tqfp144 pbga160 mc[3:0] monitoring configuration 0000 normal operation without monitoring 0001 monitor receiver 1 0010 monitor receiver 2 0011 monitor receiver 3 0100 monitor receiver 4 0101 monitor receiver 5 0110 monitor receiver 6 0111 monitor receiver 7 1000 normal operation without monitoring 1001 monitor transmitter 1 1010 monitor transmitter 2 1011 monitor transmitter 3 1100 monitor transmitter 4 1101 monitor transmitter 5 1110 monitor transmitter 6 1111 monitor transmitter 7
11 IDT82V2048S octal t1/e1 short haul liu with single ended industrial temperature ranges tdo o high-z 98 f13 tdo: jtag test data output this pin output the serial data of the jtag test. the data on tdo is clocked out of the device on the fall- ing edges of tck. tdo is a high-z output signal. it is active only when scanning of data is out. this pin should be left float when unused. tdi i pull-up 99 f12 tdi: jtag test data input this pin input the serial data of the jtag test. the data on tdi is clocked into the device on the rising edges of tck. this pin has an internal pull-up resistor and it can be left open. power supplies and grounds vddio - 17 92 g1 g14 3.3 v i/o power supply gndio - 18 91 g4 g11 i/o gnd vddt0 vddt1 vddt2 vddt3 vddt4 vddt5 vddt6 vddt7 - 44 53 56 65 116 125 128 137 n4, p4 l4, m4 l11, m11 n11, p11 a11, b11 c11, d11 c4, d4 a4, b4 3.3 v/5 v power supply for transmitter driver all vddt pins must be connected to 3.3 v or all vddt must be connected to 5 v. it is not allowed to leave any of the vddt pins open (not-connected) even if the channel is not used. for t1 applications, only 5 v vddt is supported. gndt0 gndt1 gndt2 gndt3 gndt4 gndt5 gndt6 gndt7 - 47 50 59 62 119 122 131 134 n6, p6 l6, m6 l9, m9 n9, p9 a9, b9 c9, d9 c6, d6 a6, b6 analog gnd for transmitter driver vddd vdda - 19 90 h1 h14 3.3 v digital/analog core power supply gndd gnda - 20 89 h4 h11 digital/analog core gnd others ic o 93 94 g13 h13 ic: internal connection internal use. leave it float for normal operation. table-1 pin description (continued) name type pin no. description tqfp144 pbga160
12 IDT82V2048S octal t1/e1 short haul liu with sing le ended option industrial temperature ranges 2 functional description 2.1 overview the IDT82V2048S is a fully integrat ed octal short-haul line interface unit, which contains eight transmit and receive channels for use in either t1 or e1 applications. the receiv er performs clock and data recovery. as an option, the raw sliced data (no retiming) can be output to the system. transmit equalization is implemented with low-impedance output drivers that prov ide shaped waveforms to the transformer, guar- anteeing template conformance. a selectable jitter attenuator may be placed in the receive path or the transmit path. moreover, multiple testing functions, such as error detection, loopback and jtag boundary scan are also provided. the device is optimized for flexible software control through a serial or parallel ho st mode interface. hardware control is also available. figure-1 on page 1 shows one of the eight identical channels operation. 2.2 t1/e1 mode selection t1/e1 mode selection configures the device globally. in hardware mode, the template selection pins ts[2:0], determine whether the opera- tion mode is t1 or e1 (see table-9 on page 19 ). in host mode, the register ts determines whether the operation mode is t1 or e1. 2.2.1 line interface the device supports two line interf aces: differential and single ended. a differential receive termination on rtipn and rringn is supported in host mode and hardware mode by default. a single ended receive termination on rtipn is supported in host mode only. by default, differ- ential receive termination is enabled. to enable single ended receive termination, bit srx in register e-srx has to be set. see 2.4.1 single ended receive termination . 2.2.2 system interface the system interface of each cha nnel can be configured to operate in different modes: 1. single rail interface with clock recovery. 2. dual rail interface with clock recovery. 3. dual rail interface with data recovery (that is, with raw data slicing only and without clock recovery). each signal pin on system side has multiple functions depending on which operation mode the device is in. the dual rail interface consists of tdpn 1 , tdnn, tclkn, rdpn, rdnn and rclkn. data transmitt ed from tdpn and tdnn appears on ttipn and tringn at the line interface; data received on rtipn and rringn in differential receive termination or received on rtipn in single ended receive termination at t he line interface are transferred to rdpn and rdnn while the recovered clock extracting from the received data stream outputs on rclkn. in dual rail operation, the clock/data recovery mode is selectable. dual rail interface with clock recovery shown in figure-4 is a default configuration mode. dual rail interface with data recovery is shown in figure-5 . pin rdpn and rdnn, are raw rz slice outputs and internally connected to an exor which is fed to the rclkn output for external cl ock recovery applications. in single rail mode, data transmitted from tdn appears on ttipn and tringn at the line interface. data received on rtipn and rringn in differential receive termination or received on rtipn in single ended receive termination at the line interface appears on rdn while the recov- ered clock extracting from the rece ived data stream outputs on rclkn. when the device is in single rail interface, the selectable ami or b8zs/ hdb3 line encoder/decoder is avail able and any code violation in the received data will be indicated at the cvn pin. the single rail mode has 2 sub-modes: single rail mode 1 and single rail mode 2. single rail mode 1, whose interface is composed of tdn, tclkn, rdn, cvn and rclkn, is realized by pulling pin tdnn high for more than 16 consecu- tive tclk cycles. single rail mode 2, whose interface is composed of tdn, tclkn, rdn, cvn, rclkn and b pvin, is realized by setting bit crs in register e-crs 2 and bit sing in register e-sing . the difference between them is that, in the latter mo de bipolar violation can be inserted via pin bpvin if ami line code is selected. the configuration of the hardware mode system interface is summa- rized in table-2 . the configuration of the host mode system interface is summarized in table-3. 1. the footprint ?n? (n = 0 - 7) indicates one of the eight channels. 2. the first letter ?e-? in dicates expanded register.
13 IDT82V2048S octal t1/e1 short haul liu with sing le ended option industrial temperature ranges figure-4 dual rail interface with clock recovery figure-5 dual rail in terface with data recovery jitter attenuator jitter attenuator b8zs/ hdb3/ami decoder b8zs/ hdb3/ami encoder slicer peak detector clk&data recovery (dpll) line driver waveform shaper los detector one of eight identical channels rtipn rringn ttipn tringn losn rclkn rdpn rdnn tclkn tdnn tdpn transmit all ones note: the grey blocks are bypassed and the dotted blocks are selectable. jitter attenuator b8zs/ hdb3/ami decoder b8zs/ hdb3/ami encoder slicer peak detector clk&data recovery (dpll) line driver waveform shaper los detector one of eight identical channels rtipn rringn ttipn tringn losn rclkn (rdp rdn) rdpn rdnn tclkn tdnn tdpn transmit all ones jitter attenuator note: the grey blocks are bypassed and the dotted blo cks are selectable.
14 IDT82V2048S octal t1/e1 short haul liu with sing le ended option industrial temperature ranges figure-6 single rail mode table-2 system interface conf iguration (in hardware mode) pin mclk pin tdnn interface clocked high ( 16 mclk) single rail mode 1 clocked pulse dual rail mode with clock recovery high pulse dual rail mode with data recovery. receive just slices the incoming data. transmit is determined by the status of tclkn. low pulse receiver is powered down. transmit is determined by the status of tclkn. table-3 system interface conf iguration (in host mode) pin mclk pin tdnn crsn in e-crs singn in e-sing interface clocked high 0 0 single rail mode 1 clocked pulse 0 1 single rail mode 2 clocked pulse 0 0 dual rail mode with clock recovery clocked pulse 1 0 dual rail mode with data recovery. receive just slices the incoming data. transmit is determined by the status of tclkn. high pulse - - dual rail mode with data recovery. receive just slices the incoming data. transmit is determined by the status of tclkn. low pulse - - receiver is powered down. transmit is determined by the status of tclkn. table-4 active clock edge and active level pin clke pin rdn/rdpn and cvn/rdnn pin sdo clock recovery slicer output high rclkn active high active high sclk active high low rclkn active high active low sclk active high jitter attenuator jitter attenuator b8zs/ hdb3/ami decoder slicer peak detector clk&data recovery (dpll) line driver waveform shaper los detector one of eight identical channels rtipn rringn ttipn tringn losn rclkn rdn cvn tclkn bpvin/tdnn tdn transmit all ones b8zs/ hdb3/ami encoder
15 IDT82V2048S octal t1/e1 short haul liu with sing le ended option industrial temperature ranges 2.3 clock edges the active edge of rclkn and sclk are selectable. if pin clke is high, the active edge of rclkn is the rising edge, as for sclk, that is falling edge. on the contrary, if clke is low, the active edge of rclk is the falling edge and that of sclk is rising edge. pins rdn/rdpn, cvn/ rdnn and sdo are always active high, and those output signals are clocked out on the active edge of rclkn and sclk respectively. see table-4 active clock edge and active level on page 14 for details. however, in dual rail mode without clock recovery, pin clke is used to set the active level for rdpn/rdnn raw slicing output: high for active high polarity and low for active lo w. it should be noted that data on pin sdi are always active high and ar e sampled on the rising edges of sclk. the data on pin tdn/tdpn or bpvin/tdnn are also always active high but are sampled on the fa lling edges of tclkn, despite the level on clke. 2.4 receiver in receive path with differential termination, the line signals couple into rringn and rtipn via a trans former and are converted into rz digital pulses by a data slicer. in the receive path with single ended termination (e1 75 ? ), the line signal is coupled into rtipn via a trans- former and is converted into rz di gital pulses by a data slicer. adapta- tion for attenuation is achieved using an integral peak detector that sets the slicing levels. clock and data are recovered from the received rz digital pulses by a digital phase-lock ed loop that provides jitter accom- modation. after passing through the selectable jitter attenuator, the recovered data are decoded using b8zs/hdb3 or ami line code rules and clocked out of pin rdn in single rail mode, or presented on rdpn/ rdnn in an undecoded dual rail nrz fo rmat. loss of signal, alarm indi- cation signal, line code violation and excessive zeros are detected. the presence of programmable inband l oopback codes are also detected. these various changes in status may be enabled to generate interrupts. 2.4.1 single ended receive termination the 82v2048s offers a single ended receive termination mode to enable a true single ended termination on both the primary and secondary side of the transformer. refer to figure-13 for details. single ended receive termination is only av ailable when the device is operated in host mode. to enable the single ended receive termination, bit srx in register e-srx has to be set to ?1? which will configure the corre- sponding receiver in single ended receive termination mode. 2.4.2 peak detector and slicer the slicer determines the pres ence and polarity of the received pulses. in data recovery mode, the raw positive slicer output appears on rdpn while the negative slicer output appears on rdnn. in clock and data recovery mode, the slicer output is sent to clock and data recovery circuit for abstracting re timed data and optional decoding. the slicer circuit has a built-in peak detec tor from which the slicing threshold is derived. the slicing threshold is default to 50% (typical) of the peak value. signals with an attenuation of up to 11 db (from 2.4 v) can be recov- ered by the receiver. to provide i mmunity from impulsive noise, the peak detectors are held above a minimum level of 0.1 v typically, despite the received signal level. 2.4.3 clock and data recovery the clock and data recovery is accomplished by digital phase locked loop (dpll). the dpll is clocked 16 times of the received clock rate, i.e. 24.704 mhz in t1 mode or 32.768 mhz in e1 mode. the recovered data and clock from dpll is then sent to the selectable jitter attenuator or decoder for further processing. the clock recovery and data recovery mode can be selected on a per channel basis by setting bit crsn in register e-crs . when bit crsn is defaulted to ?0?, the corresponding channel operates in data and clock recovery mode. the recovered clock is output on pin rclkn and re- timed nrz data are output on pin rd pn/rdnn in dual rail mode or on rdn in single rail mode. when bit crsn is set to ?1?, dual rail mode with data recovery is enabled in the corresponding channel and the clock recovery is bypassed. in this condition, the analog line signals are converted to rz digital bit str eams on the rdpn/rdnn pins and inter- nally connected to an exor which is fed to the rclkn output for external clock reco very applications. if mclk is pulled high, all the receivers will enter the dual rail mode with data recovery. in this case, register e-crs is ignored. 2.4.4 b8zs/hdb3/ami line code rule selectable b8zs/hdb3 and ami line coding/decoding is provided when the device is configured in single rail mode. b8zs rules for t1 and hdb3 rules for e1 are enabled by setting bit code in register gcf to ?0? or pulling pin code low. ami rule is enabled by setting bit code in register gcf to ?1? or pulling pin code high. the settings affect all eight channels. individual line code rule selection for each channel, if needed, is available by setting bit singn in register e-sing to ?1? (to activate bit coden in register e-code ) and programming bit coden to select line code rules in the corresponding channel: ?0? for b8zs/hdb3, while ?1? for ami. in this case, the value in bit code in register gcf or pin code for global control is unaffected in the corresponding channel and only affect in other channels. in dual rail mode, the decoder/encoder are bypassed. bit code in register gcf , bit coden in register e-code and pin code are ignored. the configuration of the line code rule is summarized in table-5 . 2.4.5 loss of signal (los) detection the loss of signal detector monitors the amplitude and density of the received signal on receiver line before the transformer (measured on port a, b shown in figure-12 and figure-13 ). the loss condition is reported by pulling pin losn high. at the same time, los alarm regis- ters track los condition. when los is detected or cleared, an interrupt will generate if not masked. in host mode, the detection supports the ansi t1.231 for t1 mode, itu g.775 and etsi 300 233 for e1 mode. in hardware mode, it supports the itu g.775 and ansi t1.231. table-6 summarizes the conditions of los in clock recovery mode. during los, the rdpn/rdnn continue to output the sliced data when bit aise in register gcf is set to ?0? or output all ones as ais (alarm indication signal) when bit aise is set to ?1?. the rclkn is replaced by mclk only if the bit aise is set.
16 IDT82V2048S octal t1/e1 short haul liu with sing le ended option industrial temperature ranges 2.4.6 alarm indication signal (ais) detection alarm indication signal is avail able only in host mode with clock recovery, as shown in table-7 . 2.4.7 error detection the device can detect excessive ze ros, bipolar violation and b8zs/ hdb3 code violation, as shown in figure-7 , figure-8 and figure-9 . all the three kinds of errors are r eported in both host mode and hardware mode with b8zs/hdb3 line code rule used. in host mode, the e-czer and e-codv are used to determine whether excessive zeros and code violation are reported respectively. when the device is configured in ami decoding mode, only bipolar violation can be reported. the error detection is available onl y in single rail mode in which the pin cvn/rdnn is used as er ror report output (cvn pin). the configuration and report status of error detection are summa- rized in table-8 . table-5 configuration of the line code rule hardware mode host mode code line code rule code in gcf coden in e-code singn in e-sing line code rule low all channels in b8zs/hdb3 00/1 0 all channels in b8zs/hdb3 00 1 10/1 0 all channels in ami high all channels in ami 11 1 01 1chn in ami 1 0 1 chn in b8zs/hdb3 table-6 los condition in clock recovery mode standard signal on losn ansi t1.231 for t1 g.775 for e1 etsi 300 233 for e1 los detected continuous intervals 175 32 2048 (1 ms) high amplitude (1) 1. los levels at device rtipn and rringn for differential receive te rmination and rtipn for single ended receive termination. for more detail regarding the los parameters, please refer to receiver characteristics on page 49 . differential below typical 200 mvp below typical 200 mvp below typical 200 mvp single ended below typical 158 mvp below typical 158 mvp below typical 158 mvp los cleared density 12.5% (16 marks in a sliding 128-bit period) with no more than 99 continuous zeros 12.5% (4 marks in a sliding 32-bit period) with no more than 15 continuous zeros 12.5% (4 marks in a sliding 32-bit period) with no more than 15 continuous zeros low amplitude (1) differential exceed typical 250 mvp exceed typical 250 mvp exceed typical 250 mvp single ended exceed typical 197 mvp exceed typical 197 mvp exceed typical 197mvp table-7 ais condition itu g.775 for e1 (register lac defaulted to ?0?) etsi 300 233 for e1 (register lac set to ?1?) ansi t1.231 for t1 ais detected less than 3 zeros contained in each of two consecutive 512-bit stream are received less than 3 zeros contained in a 512-bit stream are received less than 9 zeros contained in a 8192-bit stream (a ones density of 99.9% over a period of 5.3 ms) are received ais cleared 3 or more zeros contained in each of two consecutive 512-bit stream are received 3 or more zeros contained in a 512-bit stream are received 9 or more zeros contained in a 8192-bit stream are received
17 IDT82V2048S octal t1/e1 short haul liu with sing le ended option industrial temperature ranges figure-7 ami bipolar violation figure-8 hdb3 code violation & excessive zeros table-8 error detection hardware mode host mode line code pin cvn reports line code codvn in e-codv czern in e-czer pin cvn reports ami bipolar violation ami - - bipolar violation b8zs/ hdb3 bipolar violation + code violation + excessive zeros b8zs/hdb3 0 0 bipolar violation + code violation 0 1 bipolar violation + code violation + excessive zeros 1 0 bipolar violation 1 1 bipolar violation + excessive zeros bipolar violation detected bipolar violation rclkn rtipn rringn rdn cvn 1 2 3 4 5v 6 7 12 345 6 v code violation detected excessive zeros detected rclkn rtipn rringn rdn cvn code violation 4 consecutive zeros 1 2 3 4vv 5 6 12 34 56
18 IDT82V2048S octal t1/e1 short haul liu with sing le ended option industrial temperature ranges figure-9 b8zs excessive zeros 2.5 transmitter in transmit path, data in nrz format are clocked into the device on tdn and encoded by ami or b8zs/hdb 3 line code rules when single rail mode is configured or pre-encoded data in nrz format are input on tdpn and tdnn when dual rail mode is configured. the data are sampled into the device on falling edges of tclkn. jitter attenuator, if enabled, is provided with a fifo through which the data to be trans- mitted are passing. a low jitter clock is generated by an integral digital phase-locked loop and is used to read data from the fifo. the shape of the pulses are user programmable to ensure that the t1/e1 pulse template is met after the signal pass es through different cable lengths or types. bipolar violation, for di agnosis, can be inserted on pin bpvin if ami line code rule is enabled. 2.5.1 waveform shaper t1 pulse template, specified in the dsx-1 cross-connect by ansi t1.102, is illustrated in figure-10 . the device has built-in transmit wave- form templates, corresponding to 5 le vels of pre-equalization for cable of a length from 0 ft to 655 ft with each increment of 133 ft. e1 pulse template, specified in itu-t g.703, is shown in figure-11 . the device has built-in transmit wave form templates for cable of 75 ? or 120 ? . any one of the six built-in waveforms can be chosen in both hard- ware mode and host mode. in hardware mode, setting pins ts[2:0] can select the required waveform template for all the transmitters, as shown in table-9 . in host mode, the waveform template can be configured on a per-channel basis. bits tsia[2:0] in register tsia are used to select the channel and bits ts[2:0] in register ts are used to select the required waveform template. the built-in waveform shaper uses an internal high frequency clock which is 16xmclk as the clock re ference. this function will be bypassed when mclk is unavailable. figure-10 dsx-1 waveform template figure-11 cept waveform template excessive zeros detected rclkn rtipn rringn rdn cvn 8 consecutive zeros 123 1 45 67 8 2 35 46 7 8 9 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 1.2 0 250 500 750 1000 1250 time (ns) normalized amplitude -300 -200 -100 0 100 200 300 time (ns) -0.20 0.00 0.20 0.40 0.60 0.80 1.00 1.20 normalized amplitude
19 IDT82V2048S octal t1/e1 short haul liu with sing le ended option industrial temperature ranges 2.5.2 bipolar violation insertion when configured in single rail mode 2 with ami line code enabled, pin tdnn/bpvin is used as bpvi input. a low-to-high transition on this pin inserts a bipolar violation on the next available mark in the transmit data stream. sampling occurs on the falling edges of tclk. but in taos (transmit all ones) with analog loopback, remote loopback and inband loopback, the bpvi is disabled. in taos with digital loopback, the bpvi is looped back to the system side, so the data to be transmitted on ttipn and tringn are all ones with no bipolar violation. 2.6 jitter attenuator the jitter attenuator can be selected to work either in transmit path or in receive path or not used. the sele ction is accomplished by setting pin jas in hardware mode or configur ing bits jacf[1:0] in register gcf in host mode, which affects all eight channels. for applications which require line synchronization, the line clock needed to be extracted for the internal synchronization, the jitter attenu- ator is set in the receive path. another use of the jitter attenuator is to provide clock smoothing in the trans mit path for applications such as synchronous/asynchronous demultiplex ing applications. in these appli- cations, tclk will have an instant aneous frequency that is higher than the nominal t1/e1 data rate and in order to set the average long-term tclk frequency within the transmit li ne rate specifications, periods of tclk are suppressed (gapped). the jitter attenuator integrates a fifo which can accommodate a gapped tclk. in host mode, the fifo length can be 32 x 2 or 64 x 2 bits by programming bit jadp in gcf . in hardware mode, it is fixed to 64 x 2 bits. the fifo length determi nes the maximum permissible gap width (see table-10 gap width limitation ). exceeding these values will cause fifo overflow or underflow. the data is 16 or 32 bits? delay through the jitter attenuator in the corresponding transmit or receive path. the constant delay feature is crucial for the applications requiring ?hitless? switching. in host mode, bit jabw in gcf determines the jitter attenuator 3 db corner frequency (fc) for both t1 and e1. in hardware mode, the fc is fixed to 2.5 hz for t1 or 1.7 hz for e1. generally, the lower the fc is, the higher the attenuation. however, lower fc comes at the expense of increased acquisition time. therefore, the optimum fc is to optimize both the attenuation and the acquisition time. in addition, the longer fifo length results in an increased throughput delay and also influences the 3 db corner frequency. generally, it?s recommended to use the lower corner frequency and the shortest fifo length that can still meet jitter attenuation requirements. 2.7 line interface circuitry the transmit and receive interf ace rtipn/rringn and ttipn/ tringn connections provide a ma tched interface to the cable. figure- 12 and figure-13 show the appropriate external components to connect with the cable for one transmit/receive channel. table-12 summarizes the component values based on the specific application. table-9 built-in waveform template selection ts2 ts1 ts0 service clock rate cable length maximum cable loss (db) (1) 1. maximum cable loss at 772 khz. 0 0 0 e1 2.048 mhz 120 ? /75 ? cable - - 001 reserved 010 011 t1 1.544 mhz 0-133 ft. abam 0.6 1 0 0 133-266 ft. abam 1.2 1 0 1 266-399 ft. abam 1.8 1 1 0 399-533 ft. abam 2.4 1 1 1 533-655 ft. abam 3.0 table-10 gap width limitation fifo length max. gap width 64 bit 56 ui 32 bit 28 ui table-11 output jitter specification t1 e1 at&t pub 62411 itu-t g.736 gr-253-code itu-t g.742 tr-tsy-000009 itu-t g.783 etsi ctr 12/13 table-12 external components values component e1 t1 75 ? coax 120 ? twisted pair 100 ? twisted pair, vddt = 5.0 v r t 9.5 ? 1% 9.5 ? 1% 9.1 ? 1% r r 9.31 ? 1% 15 ? 1% 12.4 ? 1% cp 2200 pf 1000 pf d1 - d4 nihon inter electronics - ep05q03l, 11eqs0 3l, ec10qs04, ec10qs03l; motorola - mbr0540t1
20 IDT82V2048S octal t1/e1 short haul liu with sing le ended option industrial temperature ranges figure-12 external transmit/receive line circuitry (differential receive interface) figure-13 external transmit/receive line circuitry (single ended receive interface) 2.8 transmit driver power supply all transmit driver power supplies must be 5.0 v. in e1 mode, despite the power supply voltage, the 75 ? /120 ? lines are driven through a pair of 9.5 ? series resistors and a 1:2 transformer. in t1 mode, only 5.0 v can be selected. 100 ? lines are driven through a pair of 9.1 ? series resistors and a 1:2 transformer. to opti- mize the power consumption of the dev ice, series resistors are removed in this case. for t1 applications, only 5.0 v operation is supported. however, in harsh cable environment, series resi stors are required to improve the transmit return loss performance and protect the device from surges coupling into the device. 0.22 f ? ? ? ?? r x line 1 k ? r r r r ? ? t x line r t r t rtipn rringn tringn ttipn ? ? f gndtn vdddn vddt IDT82V2048S one of eight identical channels vddt vddt d4 d3 d2 d1 2 : 1 1 2 : 1 1 1 k ? cp 3 2 a b note: 1. pulse t1124 transformer is recommended to be used in standard (std) operating temperature range (0c to 70c), while pulse t1114 transformer is recommended to be used in extended (ext) operating temperature range is -40c to +85c. see transformer specific ations table for details. 2. typical value. adjust for actual board parasitics to obtain optimum return loss. 3. common decoupling capacitor for all vddt and gndt pins. one per chip. 68 f ?? r x line ? ? t x line r t r t rtipn rringn tringn ttipn ? ? f gndtn vdddn vddt IDT82V2048S one of eight identical channels vddt vddt d4 d3 d2 d1 2 : 1 1 2 : 1 1 19 ? cp 3 2 a note: 1. pulse t1124 transformer is recommended to be used in standar d (std) operating temperature range (0c to 70c), while pulse t1114 transformer is recommended to be used in extended (ext) operating temperature ra nge is -40c to +85c. see trans former specifications table fo r details. 2. typical value. adjust for actual board parasitics to obtain optimum return loss. 3. common decoupling capacitor for all vddt and gndt pins. one per chip. 4. the line input signal is coupled to pin rtipn with a 100 nf capacitor while pin rringn, should be ac coupled to ground thro ugh a 100 nf capacitor. 68 f 100 nf 100 nf 4 r r 1 k ? table-13 transformer specifications (1) 1. pulse t1124 transformer is recommended to be used in standard (s td) operating temperature range (0 c to 70c), while pulse t111 4 transformer is recommended to be used in extended (ext) operating temperat ure range is -40c to +85c. electrical specification @ 25c part no. turns ratio (pri: sec 2%) ocl @ 25c (mh min) l l ( h max) c w/w (pf max) package/schematic std temp. ext temp. transmit receive transmit receive transmit receive transmit receive t1124 t1114 1:2ct 1ct:2 1.2 1.2 .6 .6 35 35 tou/3
21 IDT82V2048S octal t1/e1 short haul liu with sing le ended option industrial temperature ranges 2.9 power driver failure monitor an internal power driver failu re monitor (dfmon), parallel connected with ttipn and tringn, c an detect short circuit failure between ttipn and tringn pi ns. bit scpb in register gcf decides whether the output driver short ci rcuit protection is enabled. when the short circuit protection is enabled, the driver output current is limited to a typical value: 180 map. also, register df , dfi and dfm will be available. when dfmon will detect a short circuit, register df will be set. with a short circuit failure detected and shor t circuit protection enabled, register dfi will be set and an interrupt will be generated on pin int . 2.10 transmit line side short circuit failure detection in e1 or t1 with 5 v vddt, a pair of 9.5 ? serial resistors connect with ttipn and tringn pins and limit the output current. in this case, the output current is a limited value which is always lower than the typical line short circuit current 180 map, even if the transmit line side is shorted. refer to table-12 external components values for details. 2.11 line protection in transmit side, the schottky diodes d1~d4 are required to protect the line driver and improve the des ign robustness. for differential receive interface and single ended receive interface, the line protection in receive side is different. to prot ect the receiver against current surges coupled in the device, two series resistors of 1 k ? are used for differen- tial receive interface and a series resistor of 1 k ? is used for single ended receive interface. refer to figure-12 and figure-13 . the series resistor/resistors does/do not affect the receiver sensitivity, since the receiver impedance is as high as 120 k ? typically. 2.12 hitless protection switching (hps) the IDT82V2048S transceivers incl ude an output driver with high-z feature for t1/e1 redundancy applications . this feature reduces the cost of redundancy protection by eliminating external relays. details of hps are described in relative application note. 2.13 software reset writing register rs will cause software reset by initiating about 1 s reset cycle. this operation set all the registers to their default value. 2.14 power on reset during power up, an internal rese t signal sets all the registers to default values. the power-on reset takes at least 10 s, starting from when the power supply exceeds 2/3 vdda. 2.15 power down each transmit channel will be powered down by pulling pin tclkn low for more than 64 mclk cycles (i f mclk is available) or about 30 s (if mclk is not available). in hos t mode, each transmit channel will also be powered down by setting bit tpdnn in register e-tpdn to ?1?. all the receivers will be power ed down when mclk is low. when mclk is clocked or high, se tting bit rpdnn in register e-rpdn to ?1? will configure the corresponding receiver to be powered down. 2.16 interface with 5 v logic the IDT82V2048S can interface direct ly with 5 v ttl family devices. the internal input pads are tolerant to 5 v output from ttl and cmos family devices. 2.17 loopback mode the device provides five different diagnostic loopback configurations: digital loopback, analog loopback, remote loopback, dual loopback and inband loopback. in host mode, t hese functions are implemented by programming the registers dlb , alb , rlb and inband loopback register group respectively. in hardware mode, only analog loopback and remote loopback can be selected by pin lpn. 2.17.1 digital loopback by programming the bits of register dlb , each channel of the device can be configured in local digital loopback. in this configuration, the data and clock to be transmitted, after passing the encoder, are looped back to jitter attenuator (if enabled) and decoder in the receive path, then output on rclkn, rdn/rdpn and cvn/rdnn. the data to be transmitted are still output on ttipn and tringn while the data received on rtipn and rringn are ignor ed. the loss detector is still in use. figure-14 shows the process. during digital loopback, the received signal on the receive line is still monitored by the los detector (see 2.4.5 loss of signal (los) detec- tion for details). in case of a los condition and ais insertion enabled, all ones signal will be output on rdpn/rdnn. with atao enabled, all ones signal will be also output on ttipn/tringn. ais insertion can be enabled by setting aise bit in register gcf and atao can be enabled by setting register atao (default disabled). 2.17.2 analog loopback by programming the bits of register alb or pulling pin lpn high, each channel of the device can be configured in analog loopback. in this configuration, the data to be transmitted output from the line driver are internally looped back to the slicer and peak detector in the receive path and output on rclkn, rdn/rdpn and cvn/rdnn. the data to be transmitted are still output on ttipn and tringn while the data received on rtipn and rringn are ignored. the los detector (see 2.4.5 loss of signal (los) detection for details) is still in use and moni- tors the internal looped back data. if a los condition on tdpn/tdnn is expected during analog loopback, at ao should be disabled (default). figure-15 shows the process. the ttipn and rtipn, tringn and rringn cannot be connected directly to do the external anal og loopback test. line impedance loading is required to conduct the external analog loopback test. 2.17.3 remote loopback by programming the bits of register rlb or pulling pin lpn low, each channel of the device can be set in remote loopback. in this configura- tion, the data and clock recovered by the clock and data recovery circuits are looped to waveform shaper and output on ttipn and tringn. the jitter attenuator is also included in loopback when enabled in the transmit or receive path. the received data and clock are still output on rclkn, rdn/rdpn and cvn/rdnn while the data to be trans- mitted on tclkn, tdn/tdpn and bpv in/tdnn are ignored. the los detector is still in use. figure-16 shows the process.
22 IDT82V2048S octal t1/e1 short haul liu with sing le ended option industrial temperature ranges 2.17.4 dual loopback dual loopback mode is set by setting bit dlbn in register dlb and bit rlbn in register rlb to ?1?. in this configuration, after passing the encoder, the data and clock to be transmitted are looped back to decoder directly and output on rclk n, rdn/rdpn and cvn/rdnn. the recovered data from rtipn and rringn are looped back to waveform shaper through ja (if selected) and output on ttipn and tringn. the los detector is still in use. figure-17 shows the process. 2.17.5 transmit all ones (taos) in hardware mode, the taos mode is set by pulling pin tclkn high for more than 16 mclk cycles. in host mode, taos mode is set by programming register tao . in addition, automatic taos signals are inserted by setting register atao when loss of signal occurs. note that the taos generator adopts mclk as a timing reference. in order to assure that the output frequency is within specified limits, mclk must have the applicable stability. the taos mode, the taos mode with digital loopback and the taos mode with analog loopback are shown in figure-18 , figure-19 and figure-20 . figure-14 digital loopback figure-15 analog loopback jitter attenuator jitter attenuator b8zs/ hdb3/ami decoder b8zs/ hdb3/ami encoder slicer peak detector clk&data recovery (dpll) line driver waveform shaper los detector digital loopback one of eight identical channels rtipn rringn ttipn tringn losn rclkn rdn/rdpn cvn/rdnn tclkn bpvin/tdnn tdn/tdpn transmit all ones jitter attenuator jitter attenuator b8zs/ hdb3/ami decoder b8zs/ hdb3/ami encoder analog loopback slicer peak detector clk&data recovery (dpll) line driver waveform shaper los detector one of eight identical channels rtipn rringn ttipn tringn losn rclkn rdn/rdpn cvn/rdnn tclkn bpvin/tdnn tdn/tdpn transmit all ones
23 IDT82V2048S octal t1/e1 short haul liu with sing le ended option industrial temperature ranges figure-16 remote loopback figure-17 dual loopback figure-18 taos data path jitter attenuator jitter attenuator b8zs/ hdb3/ami decoder b8zs/ hdb3/ami encoder remote/ inband loopback slicer peak detector clk&data recovery (dpll) line driver waveform shaper iblc detector los detector iblc generator one of eight identical channels rtipn rringn ttipn tringn losn rclkn rdn/rdpn cvn/rdnn tclkn bpvin/tdnn tdn/tdpn transmit all ones jitter attenuator jitter attenuator b8zs/ hdb3/ami decoder b8zs/ hdb3/ami encoder slicer peak detector clk&data recovery (dpll) line driver waveform shaper los detector one of eight identical channels rtipn rringn ttipn tringn losn rclkn rdn/rdpn cvn/rdnn tclkn bpvin/tdnn tdn/tdpn transmit all ones jitter attenuator jitter attenuator b8zs/ hdb3/ami decoder b8zs/ hdb3/ami encoder slicer peak detector clk&data recovery (dpll) line driver waveform shaper los detector one of eight identical channels rtipn rringn ttipn tringn losn rclkn rdn/rdpn cvn/rdnn tclkn bpvin/tdnn tdn/tdpn transmit all ones
24 IDT82V2048S octal t1/e1 short haul liu with sing le ended option industrial temperature ranges figure-19 taos with digital loopback figure-20 taos with analog loopback 2.17.6 inband loopback inband loopback is a function that facilitates the system remote diagnosis. when this function is enabled, the chip will detect or generate the inband loopback code. there are two kinds of inband loopback code: activate code and deactivate code. if the activate code is received from the far end in a continuous 5.1 second, the chip will auto- matically go into remote loopback mode (shown in figure-16 ). if the deactivate code is received from the far end in a continuous 5.1 second, the chip quits from the remote loopback mode. the chip can send the activate code and deactiva te code to the far end. two func- tion blocks: iblc detector (inband loopback code detector) and iblc generator (inband loopback code generator), realize the inband loop- back. the detection of inband loopback code is enabled by bit lbde in register e-lbcf . if bit albe in register e-lbcf is set to ?1?, the chip will automatically go into or quit from the remote loopback mode based on the receipt of inband loopback code. the length of the activate code is defined in bits lbal[1:0] in register e-lbcf ; and the length of the deac- tivate code is defined in bits lbdl[1:0] in register e-lbcf . the pattern of the activate code is defined in register e-lbac , and the pattern of the deactivate code is defined in register e-lbdc . the above settings are globally effective for all the eight channels. the presence of inband loopback code in each channel is reflected timely in register e-lbs . any transition of each bit in register e-lbs will be reflected in register e- lbi , and if enabled in register e-lbm , will generate an interrupt. the required sequence of programming the inband loopback code detec- tion is: first, set registers e-lbac and e-lbdc , followed by register e- lbm . finally, to activate inband loopback detection, set register e- lbcf . the inband loopback code generator use the same registers as the inband loopback detector to define the length and pattern of activate code and deactivate code. the length and pattern of the generated activate code and deactivate code can be different from the detected activate code and deactivate code. register e-lbgs determines sending activate code or deac tivate code, and register e-lbge acts as a switch to start or stop the sending of inband loopback code to the selected channels. before sending inband loopback code, users should be sure that registers e-lbcf , e-lbac , e-lbdc and e-lbsg jitter attenuator jitter attenuator b8zs/ hdb3/ami decoder b8zs/ hdb3/ami encoder slicer peak detector clk&data recovery (dpll) line driver waveform shaper los detector one of eight identical channels rtipn rringn ttipn tringn losn rclkn rdn/rdpn cvn/rdnn tclkn bpvin/tdnn tdn/tdpn transmit all ones jitter attenuator b8zs/ hdb3/ami decoder b8zs/ hdb3/ami encoder slicer peak detector clk&data recovery (dpll) line driver waveform shaper los detector one of eight identical channels rtipn rringn ttipn tringn losn rclkn rdn/rdpn cvn/rdnn tclkn bpvin/tdnn tdn/tdpn transmit all ones
25 IDT82V2048S octal t1/e1 short haul liu with sing le ended option industrial temperature ranges are configured properly. the require d sequence for configuring the inband loopback generator is: first, set registers e-lbac and e-lbdc , followed by register e-lbcf . then, to select the inband loopback generator set registers e-lbgs and then e-lbge . the inband loopback detection and the inband loopback genera- tion can not be used simultaneously. example: 5-bit loop-up/loop-down detection (w/o interrupts): (see note in register description for e-lbac ) loop-up code: 11000 loop-down code: 11100 set (in this order) e-lbac (0x09) = 0xc6 (11000110) e-lbdc (0x0a) = 0xe7 (11100111) e-lbcf (0x08) = 0x30 example: 5-bit loop-up/loop-down activation on channel 1 (w/o interrupts): loop-up code: 11000 loop-down code: 11100 set (in this order) e-lbac (0x09) = 0xc6 (11000110) e-lbdc (0x0a) = 0xe7 (11100111) e-lbcf (0x08) = 0x00 e-lbgs (0x0e) = 0x00 e-lbge (0x0f) = 0x02 2.18 host interface the host interface provides access to read and write the registers in the device. the interface consists of serial host interface and parallel host interface. by pulling pin mode2 to vddio/2 or high, the device can be set to work in serial mode and in parallel mode respectively. 2.18.1 parallel host interface the interface is compatible with motorola and intel host. pins mode1 and mode0 are used to select the operating mode of the parallel host interface. when pin mode1 is pulled low, the host uses separate address bus and data bus. when high, multiplexed address/ data bus is used. when pin mode0 is pulled low, the parallel host inter- face is configured for motorola compatible hosts. when pin mode0 is pulled high, the parallel host interface is configured for intel compatible hosts. see table-1 pin description for more details. the host interface pins in each operation mode is tabulated in table-14 : figure-21 serial host mode timing 2.18.2 serial host interface by pulling pin mode2 to vddio/2, the device operates in the serial host mode. in this mode, the regist ers are accessible through a 16-bit word which contains an 8-bit command/address byte (bit r/ w and 5- address-bit a1~a5, a6 and a7 bits are ignored) and a subsequent 8-bit data byte (d7~d0), as shown in figure-21 . when bit r/ w is set to ?1?, data is read out from pin sdo. when bit r/ w is set to ?0?, data on pin sdi is written into the register w hose address is indicated by address bits a5~a1. see figure-21 serial host mode timing . table-14 parallel host interface pins mode[2:0] host interface generic control, data and output pin 100 non-multiplexed motorola interface cs , ack , ds , r/ w , as , a[4:0], d[7:0], int 101 non-multiplexed intel interface cs , rdy, wr , rd , ale, a[4:0], d[7:0], int 110 multiplexed motorola interface cs , ack , ds , r/ w , as , ad[7:0], int 111 multiplexed intel interface cs , rdy, wr , rd , ale, ad[7:0], int a1 a3 a2 a4 a5 a6 d0 d1 d2 d3 d4 d5 d6 d7 r/ w d0 d1 d2 d3 d4 d5 d6 d7 a7 input data byte address/command byte high impedance driven while r/ w =1 sdi sdo sclk cs 1 22 1. while r/ w =1, read from IDT82V2048S; while r/ w =0, write to IDT82V2048S. 2. ignored.
26 IDT82V2048S octal t1/e1 short haul liu with sing le ended option industrial temperature ranges 2.19 interrupt handling 2.19.1 interrupt sources there are four kinds of interrupt sources: 1. status change in register los . the analog/digital loss of signal detector continuously monitors the received signal to update the specific bit in register los which indicates presence or absence of a los condition. 2. status change in register df . the automatic power driver circuit continuously monitors the output drivers signal to update the specific bit in register dfm which indicates presence or absence of an output driver short circuit condition. 3. status change in register ais . the ais detector monitors the received signal to update the specific bit in register ais which indicates presence or absence of a ais condition. 4. status change in register e-lbs . the iblc detector monitors the inband loopback activation or deactivation code in received signal to update the specific bit in register e-lbs which indicates presence or absence of an inband loopback condition. figure-22 interru pt service routine 2.19.2 interrupt enable the IDT82V2048S provides a latched interrupt output ( int ) and the four kinds of interrupts are all repor ted by this pin. when the interrupt mask register ( losm , dfm , aism and e-lbm ) is set to ?1?, the interrupt status register ( losi , dfi , aisi and e-lbi ) is enabled respectively. whenever there is a transition (?0? to ?1? or ?1? to ?0?) in the corresponding status register, the interrupt status register will change into ?1?, which means an interrupt occurs, and there will be a high to low transition on int pin. an external pull-up resistor of approximately 10 k ? is required to support the wire-or operation of int . when any of the four interrupt mask registers is set to ?0? (the power -on default value is ?0?), the corre- sponding interrupt status register is disabled and the transition on status register is ignored. 2.19.3 interrupt clearing when an interrupt occurs, the interrupt status registers: losi , dfi , aisi and e-lbi , are read to identify the inte rrupt source. these registers will be cleared to ?0? after the corresponding status registers: los , df , ais and e-lbs are read. the status registers will be cleared once the corresponding conditions are met. pin int is pulled high when there is no pending interrupt left. the interrupt handling in the interrupt service routine is showed in figure-22 . 2.20 g.772 monitoring the eight channels of IDT82V2048S c an all be configured to work as regular transceivers. in applicati ons using only seven channels (chan- nels 1 to 7), channel 0 is configured to non-intrusively monitor any of the other channels? inputs or outputs on t he line side. the monitoring is non- intrusive per itu-t g.772. figure-23 shows the monitoring principle. the receiver path or transmitter path to be monitored is configured by pins mc[3:0] in hardwar e mode or by register pmon in host mode. the monitored signal goes thr ough the clock and data recovery circuit of channel 0. the monitor ed clock can output on rclk0 which can be used as a timing interfaces derived from e1 signal. the moni- tored data can be observed digitally at the output pins rclk0, rd0/ rdp0 and rdn0. los detector is still in use in channel 0 for the moni- tored signal. in monitoring mode, channel 0 c an be configured in remote loop- back. the signal which is being monitored will output on ttip0 and tring0. the output signal can then be connected to a standard test equipment with an e1 electrical in terface for non-intrusive monitoring. service the interrupt read interrupt status register read corresponding status register interrupt allowed interrupt condition exist? yes no
27 IDT82V2048S octal t1/e1 short haul liu with sing le ended option industrial temperature ranges figure-23 monitoring principle jitter attenuator jitter attenuator b8zs/ hdb3/ami decoder b8zs/ hdb3/ami encoder slicer peak detector clk&data recovery (dpll) line driver waveform shaper los detector channel n ( 7 > n > 1 ) rtipn rringn ttipn tringn losn rclkn rdn/rdpn cvn/rdnn tclkn bpvin/tdnn tdn/tdpn g.772 monitor transmit all ones jitter attenuator jitter attenuator b8zs/ hdb3/ami decoder b8zs/ hdb3/ami encoder remote loopback slicer peak detector clk&data recovery (dpll) line driver waveform shaper los detector channel 0 los0 rclk0 rd0/rdp0 cv0/rdn0 tclk0 bpvi0/tdn0 td0/tdp0 transmit all ones rtip0 rring0 ttip0 tring0
28 IDT82V2048S octal t1/e1 short haul liu with sing le ended option industrial temperature ranges 3 programming information 3.1 register list and map there are 23 primary registers (inc luding an address pointer control register and 16 expanded registers in the device). whatever the control interface is, 5 address bits are used to set the registers. in non-multiplexed paralle l interface mode, the five dedicated address bits are a[4:0]. in multiplexed parallel interface mode, ad[4:0] carries the address information. in se rial interface mode, a[5:1] are used to address the register. the register addp , addressed as 11111 or 1f hex, switches between primary registers bank and expanded registers bank. by setting the register addp to ?aah?, the 5 address bits point to the expanded register bank, that is, the expanded registers ar e available. by clearing register addp , the primary registers are available. primary registers, whose addresse s are 16h to 1eh, are reserved. expanded registers, whose addresses are 10h to 1eh, are used for test and must be set to ?0? (default). table-15 primary register list address register r/w explanation hex serial interface a7-a1 parallel interface a7-a0 00 xx00000 xxx00000 id r device id register 01 xx00001 xxx00001 alb r/w analog loopback configuration register 02 xx00010 xxx00010 rlb r/w remote loopback configuration register 03 xx00011 xxx00011 tao r/w transmit all ones configuration register 04 xx00100 xxx00100 los r loss of signal status register 05 xx00101 xxx00101 df r driver fault status register 06 xx00110 xxx00110 losm r/w los interrupt mask register 07 xx00111 xxx00111 dfm r/w driver fault interrupt mask register 08 xx01000 xxx01000 losi r los interrupt status register 09 xx01001 xxx01001 dfi r driver fault interrupt status register 0a xx01010 xxx01010 rs w software reset register 0b xx01011 xxx01011 pmon r/w performance monitor configuration register 0c xx01100 xxx01100 dlb r/w digital loopback configuration register 0d xx01101 xxx01101 lac r/w los/ais criteria configuration register 0e xx01110 xxx01110 atao r/w automatic taos configuration register 0f xx01111 xxx01111 gcf r/w global configuration register 10 xx10000 xxx10000 tsia r/w indirect address register for transmit template select 11 xx10001 xxx10001 ts r/w transmit template select register 12 xx10010 xxx10010 oe r/w output enable configuration register 13 xx10011 xxx10011 ais r ais status register 14 xx10100 xxx10100 aism r/w ais interrupt mask register 15 xx10101 xxx10101 aisi r ais interrupt status register 16 xx10110 xxx10110 reserved 17 xx10111 xxx10111 18 xx11000 xxx11000 19 xx11001 xxx11001 1a xx11010 xxx11010 1b xx11011 xxx11011 1c xx11100 xxx11100 1d xx11101 xxx11101 1e xx11110 xxx11110 1f xx11111 xxx11111 addp r/w address pointer control register for switching between primary register bank and expanded register bank
29 IDT82V2048S octal t1/e1 short haul liu with sing le ended option industrial temperature ranges table-16 expanded (indirect address mode) register list address register r/w explanation hex serial interface a7-a1 parallel interface a7-a0 00 xx00000 xxx00000 e-sing r/w single rail mode setting register 01 xx00001 xxx00001 e-code r/w encoder/decoder selection register 02 xx00010 xxx00010 e-crs r/w clock recovery enable/disable register 03 xx00011 xxx00011 e-rpdn r/w receiver n powerdown enable/disable register 04 xx00100 xxx00100 e-tpdn r/w transmitter n powerdown enable/disable register 05 xx00101 xxx00101 e-czer r/w consecutive zero detect enable/disable register 06 xx00110 xxx00110 e-codv r/w code violation detect enable/disable register 07 xx00111 xxx00111 e-srx r/w single ended receive termination enable/disable register 08 xx01000 xxx01000 e-lbcf r/w inband loopback configuration register 09 xx01001 xxx01001 e-lbac r/w inband loopback activation code register 0a xx01010 xxx01010 e-lbdc r/w inband loopback deactivation code register 0b xx01011 xxx01011 e-lbs r inband loopback code receive status register 0c xx01100 xxx01100 e-lbm r/w inband loopback interrupt mask register 0d xx01101 xxx01101 e-lbi r inband loopback interrupt status register 0e xx01110 xxx01110 e-lbgs r/w inband loopback activate/deactivate code generator selection register 0f xx01111 xxx01111 e-lbge r/w inband loopback activate/deactivate code generator enable register 10 xx10000 xxx10000 test 11 xx10001 xxx10001 12 xx10010 xxx10010 13 xx10011 xxx10011 14 xx10100 xxx10100 15 xx10101 xxx10101 16 xx10110 xxx10110 17 xx10111 xxx10111 18 xx11000 xxx11000 19 xx11001 xxx11001 1a xx11010 xxx11010 1b xx11011 xxx11011 1c xx11100 xxx11100 1d xx11101 xxx11101 1e xx11110 xxx11110 1f xx11111 xxx11111 addp r/w address pointer control register for sw itching between primary register bank and expanded register bank
30 IDT82V2048S octal t1/e1 short haul liu with sing le ended option industrial temperature ranges table-17 primary register map register address r/w default bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 id 00h r default id 7 r 0 id 6 r 0 id 5 r 0 id 4 r 1 id 3 r 0 id 2 r 0 id 1 r 0 id 0 r 0 alb 01h r/w default alb 7 r/w 0 alb 6 r/w 0 alb 5 r/w 0 alb 4 r/w 0 alb 3 r/w 0 alb 2 r/w 0 alb 1 r/w 0 alb 0 r/w 0 rlb 02h r/w default rlb 7 r/w 0 rlb 6 r/w 0 rlb 5 r/w 0 rlb 4 r/w 0 rlb 3 r/w 0 rlb 2 r/w 0 rlb 1 r/w 0 rlb 0 r/w 0 tao 03h r/w default tao 7 r/w 0 tao 6 r/w 0 tao 5 r/w 0 tao 4 r/w 0 tao 3 r/w 0 tao 2 r/w 0 tao 1 r/w 0 tao 0 r/w 0 los 04h r default los 7 r 0 los 6 r 0 los 5 r 0 los 4 r 0 los 3 r 0 los 2 r 0 los 1 r 0 los 0 r 0 df 05h r default df 7 r 0 df 6 r 0 df 5 r 0 df 4 r 0 df 3 r 0 df 2 r 0 df 1 r 0 df 0 r 0 losm 06h r/w default losm 7 r/w 0 losm 6 r/w 0 losm 5 r/w 0 losm 4 r/w 0 losm 3 r/w 0 losm 2 r/w 0 losm 1 r/w 0 losm 0 r/w 0 dfm 07h r/w default dfm 7 r/w 0 dfm 6 r/w 0 dfm 5 r/w 0 dfm 4 r/w 0 dfm 3 r/w 0 dfm 2 r/w 0 dfm 1 r/w 0 dfm 0 r/w 0 losi 08h r default losi 7 r 0 losi 6 r 0 losi 5 r 0 losi 4 r 0 losi 3 r 0 losi 2 r 0 losi 1 r 0 losi 0 r 0 dfi 09h r default dfi 7 r 0 dfi 6 r 0 dfi 5 r 0 dfi 4 r 0 dfi 3 r 0 dfi 2 r 0 dfi 1 r 0 dfi 0 r 0 rs 0ah w default rs 7 w 1 rs 6 w 1 rs 5 w 1 rs 4 w 1 rs 3 w 1 rs 2 w 1 rs 1 w 1 rs 0 w 1 pmon 0bh r/w default - r/w 0 - r/w 0 - r/w 0 - r/w 0 mc 3 r/w 0 mc 2 r/w 0 mc 1 r/w 0 mc 0 r/w 0 dlb 0ch r/w default dlb 7 r/w 0 dlb 6 r/w 0 dlb 5 r/w 0 dlb 4 r/w 0 dlb 3 r/w 0 dlb 2 r/w 0 dlb 1 r/w 0 dlb 0 r/w 0 lac 0dh r/w default lac 7 r/w 0 lac 6 r/w 0 lac 5 r/w 0 lac 4 r/w 0 lac 3 r/w 0 lac 2 r/w 0 lac 1 r/w 0 lac 0 r/w 0 atao 0eh r/w default atao 7 r/w 0 atao 6 r/w 0 atao 5 r/w 0 atao 4 r/w 0 atao 3 r/w 0 atao 2 r/w 0 atao 1 r/w 0 atao 0 r/w 0 gcf 0fh r/w default - r/w 0 aise r/w 0 scpb r/w 0 code r/w 0 jadp r/w 0 jabw r/w 0 jacf 1 r/w 0 jacf 0 r/w 0
31 IDT82V2048S octal t1/e1 short haul liu with sing le ended option industrial temperature ranges tsia 10 hex r/w default - r/w 0 - r/w 0 - r/w 0 - r/w 0 - r/w 0 tsia 2 r/w 0 tsia 1 r/w 0 tsia 0 r/w 0 ts 11 hex r/w default - r/w 0 - r/w 0 - r/w 0 - r/w 0 - r/w 0 ts 2 r/w 0 ts 1 r/w 0 ts 0 r/w 0 oe 12 hex r/w default oe 7 r/w 0 oe 6 r/w 0 oe 5 r/w 0 oe 4 r/w 0 oe 3 r/w 0 oe 2 r/w 0 oe 1 r/w 0 oe 0 r/w 0 ais 13 hex r default ais 7 r 0 ais 6 r 0 ais 5 r 0 ais 4 r 0 ais 3 r 0 ais 2 r 0 ais 1 r 0 ais 0 r 0 aism 14 hex r/w default aism 7 r/w 0 aism 6 r/w 0 aism 5 r/w 0 aism 4 r/w 0 aism 3 r/w 0 aism 2 r/w 0 aism 1 r/w 0 aism 0 r/w 0 aisi 15 hex r default aisi 7 r 0 aisi 6 r 0 aisi 5 r 0 aisi 4 r 0 aisi 3 r 0 aisi 2 r 0 aisi 1 r 0 aisi 0 r 0 addp 1f hex r/w default addp 7 r/w 0 addp 6 r/w 0 addp 5 r/w 0 addp 4 r/w 0 addp 3 r/w 0 addp 2 r/w 0 addp 1 r/w 0 addp 0 r/w 0 table-17 primary register map (continued) register address r/w default bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
32 IDT82V2048S octal t1/e1 short haul liu with sing le ended option industrial temperature ranges table-18 expanded (indirect address mode) register map register address r/w default bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 e-sing 00h r/w default sing 7 r/w 0 sing 6 r/w 0 sing 5 r/w 0 sing 4 r/w 0 sing 3 r/w 0 sing 2 r/w 0 sing 1 r/w 0 sing 0 r/w 0 e-code 01h r/w default code 7 r/w 0 code 6 r/w 0 code 5 r/w 0 code 4 r/w 0 code 3 r/w 0 code 2 r/w 0 code 1 r/w 0 code 0 r/w 0 e-crs 02h r/w default crs 7 r/w 0 crs 6 r/w 0 crs 5 r/w 0 crs 4 r/w 0 crs 3 r/w 0 crs 2 r/w 0 crs 1 r/w 0 crs 0 r/w 0 e-rpdn 03h r/w default rpdn 7 r/w 0 rpdn 6 r/w 0 rpdn 5 r/w 0 rpdn 4 r/w 0 rpdn 3 r/w 0 rpdn 2 r/w 0 rpdn 1 r/w 0 rpdn 0 r/w 0 e-tpdn 04h r/w default tpdn 7 r/w 0 tpdn 6 r/w 0 tpdn 5 r/w 0 tpdn 4 r/w 0 tpdn 3 r/w 0 tpdn 2 r/w 0 tpdn 1 r/w 0 tpdn 0 r/w 0 e-czer 05h r/w default czer 7 r/w 0 czer 6 r/w 0 czer 5 r/w 0 czer 4 r/w 0 czer 3 r/w 0 czer 2 r/w 0 czer 1 r/w 0 czer 0 r/w 0 e-codv 06h r/w default codv 7 r/w 0 codv 6 r/w 0 codv 5 r/w 0 codv 4 r/w 0 codv 3 r/w 0 codv 2 r/w 0 codv 1 r/w 0 codv 0 r/w 0 e-srx 07h r/w default srx 7 r/w 0 srx 6 r/w 0 srx 5 r/w 0 srx 4 r/w 0 srx 3 r/w 0 srx 2 r/w 0 srx 1 r/w 0 srx 0 r/w 0 e-lbcf 08h r/w default - r/w 0 - r/w 0 lbde r/w 0 albe r/w 0 lbal 1 r/w 0 lbal 0 r/w 0 lbdl 1 r/w 0 lbdl 0 r/w 0 e-lbac 09h r/w default lbac 7 r/w 0 lbac 6 r/w 0 lbac 5 r/w 0 lbac 4 r/w 0 lbac 3 r/w 0 lbac 2 r/w 0 lbac 1 r/w 0 lbac 0 r/w 0 e-lbdc 0ah r/w default lbdc 7 r/w 0 lbdc 6 r/w 0 lbdc 5 r/w 0 lbdc 4 r/w 0 lbdc 3 r/w 0 lbdc 2 r/w 0 lbdc 1 r/w 0 lbdc 0 r/w 0 e-lbs 0bh r default lbs 7 r 0 lbs 6 r 0 lbs 5 r 0 lbs 4 r 0 lbs 3 r 0 lbs 2 r 0 lbs 1 r 0 lbs 0 r 0 e-lbm 0ch r/w default lbm 7 r/w 0 lbm 6 r/w 0 lbm 5 r/w 0 lbm 4 r/w 0 lbm 3 r/w 0 lbm 2 r/w 0 lbm 1 r/w 0 lbm 0 r/w 0 e-lbi 0dh r/w default lbi 7 r 0 lbi 6 r 0 lbi 5 r 0 lbi 4 r 0 lbi 3 r 0 lbi 2 r 0 lbi 1 r 0 lbi 0 r 0 e-lbgs 0eh r/w default lbgs 7 r/w 0 lbgs 6 r/w 0 lbgs 5 r/w 0 lbgs 4 r/w 0 lbgs 3 r/w 0 lbgs 2 r/w 0 lbgs 1 r/w 0 lbgs 0 r/w 0 e-lbge 0fh r/w default lbge 7 r/w 0 lbge 6 r/w 0 lbge 5 r/w 0 lbge 4 r/w 0 lbge 3 r/w 0 lbge 2 r/w 0 lbge 1 r/w 0 lbge 0 r/w 0 addp 1fh r/w default addp 7 r/w 0 addp 6 r/w 0 addp 5 r/w 0 addp 4 r/w 0 addp 3 r/w 0 addp 2 r/w 0 addp 1 r/w 0 addp 0 r/w 0
33 IDT82V2048S octal t1/e1 short haul liu with sing le ended option industrial temperature ranges 3.2 register description 3.2.1 primary registers id: device id register (r, address = 00h) symbol position default description id[7:0] id.7-0 10h an 8-bit word is pre-set into the device as the identification and revision number. this number is different with the functiona l changes and is mask programmed. alb: analog loopback configuration r egister (r/w, address = 01h) symbol position default description alb[7:0] alb.7-0 00h 0 = normal operation. (default) 1 = analog loopback enabled. rlb: remote loopback configuration register (r/w, address = 02h) symbol position default description rlb[7:0] rlb.7-0 00h 0 = normal operation. (default) 1 = remote loopback enabled. tao : transmit all ones configurati on register (r/w, address = 03h) symbol position default description tao[7:0] tao.7-0 00h 0 = normal operation. (default) 1 = transmit all ones. los: loss of signal status r egister (r, address = 04h) symbol position default description los[7:0] los.7-0 00h 0 = normal operation. (default) 1 = loss of signal detected. df: driver fault status regi ster (r, address = 05h) symbol position default description df[7:0] df.7-0 00h 0 = normal operation. (default) 1 = driver fault detected. losm: loss of signal interrupt mask register (r/w, address = 06h) symbol position default description losm[7:0] losm.7-0 00h 0 = los interrupt is not allowed. (default) 1 = los interrupt is allowed. dfm: driver fault interrupt mask register (r/w, address = 07h) symbol position default description dfm[7:0] dfm.7-0 00h 0 = driver fault interrupt not allowed. (default) 1 = driver fault interrupt allowed. losi: loss of signal interrupt status register (r, address = 08h) symbol position default description losi[7:0] losi.7-0 00h 0 = (default). or after a los read operation. 1 = any transition on losn (corresponding losmn is set to ?1?).
34 IDT82V2048S octal t1/e1 short haul liu with sing le ended option industrial temperature ranges dfi: driver fault interrupt status register (r, address = 09h) symbol position default description dfi[7:0] dfi.7-0 00h 0 = (default). or after a df read operation. 1 = any transition on dfn (corresponding dfmn is set to ?1?). rs: software reset register (w, address = 0ah) symbol position default description rs[7:0] rs.7-0 ffh writing to this register will not change the content in this register but initiate a 1 s reset cycle, which means all the registers in the device are set to their default values. pmon: performance monitor configurati on register (r/w, address = 0bh) symbol position default description - pmon.7-4 0000 0 = normal operation. (default) 1 = reserved. mc[3:0] pmon.3-0 0000 0000 = normal operation without monitoring (default) 0001 = monitor receiver 1 0010 = monitor receiver 2 0011 = monitor receiver 3 0100 = monitor receiver 4 0101 = monitor receiver 5 0110 = monitor receiver 6 0111 = monitor receiver 7 1000 = normal operation without monitoring 1001 = monitor transmitter 1 1010 = monitor transmitter 2 1011 = monitor transmitter 3 1100 = monitor transmitter 4 1101 = monitor transmitter 5 1110 = monitor transmitter 6 1111 = monitor transmitter 7 dlb : digital loopback configuration r egister (r/w, address = 0ch) symbol position default description dlb[7:0] dlb.7-0 00h 0 = normal operation. (default) 1 = digital loopback enabled. lac: los/ais criteria configuration register (r/w, address = 0dh) symbol position default description lac[7:0] lac.7-0 00h for e1 mode, the criterion is selected as below: 0 = g.775 (default) 1 = etsi 300 233 for t1 mode, the criterion meets t1.231. atao : automatic taos configuration register (r/w, address = 0eh) symbol position default description atao[7:0] atao.7-0 00h 0 = no automatic transmit all ones. (default) 1 = automatic transmit all ones to the line side during los.
35 IDT82V2048S octal t1/e1 short haul liu with sing le ended option industrial temperature ranges gcf: global configuration regist er (r/w, address = 0fh) symbol position default description -gcf.70 0 = normal operation. 1 = reserved. aise gcf.6 0 0 = ais insertion to the system side disabled on los. 1 = ais insertion to the system side enabled on los. scpb gcf.5 0 0 = short circuit protection is enabled. 1 = short circuit protection is disabled. code gcf.4 0 0 = b8zs/hdb3 encoder/decoder enabled. 1 = ami encoder/decoder enabled. jadp gcf.3 0 jitter attenuator depth select 0 = 32-bit fifo (default) 1 = 64-bit fifo jabw gcf.2 0 jitter transfer function bandwidth select 0 = 2.5 hz (t1); 1.7 hz (e1) (default) 1 = 5 hz; 6.5 hz jacf[1:0] gcf.1-0 00 jitter attenuator configuration 00 = ja not used. (default) 01 = ja in transmit path 10 = ja not used. 11 = ja in receive path tsia: indirect address register for transmit temp late select registers (r/w, address = 10h) symbol position default description - tsia.7-3 00000 0 = normal operation. (default) 1 = reserved. tsia[2:0] tsia.2-0 000 000 = channel 0 (default) 001 = channel 1 010 = channel 2 011 = channel 3 100 = channel 4 101 = channel 5 110 = channel 6 111 = channel 7 ts: transmit template select register (r/w, address = 11h) symbol position default description - ts.7-3 00000 0 = normal operation. (default) 1 = reserved. ts[2-0] ts.2-0 000 ts[2:0] select one of eight built-in transmit template for different applications. ts[2:0] mode cable length 000 e1 75 ? coaxial cable/120 ? twisted pair cable. 001 reserved. 010 011 t1 0 - 133 ft. 100 t1 133 - 266 ft. 101 t1 266 - 399 ft. 110 t1 399 - 533 ft. 111 t1 533 - 655 ft. oe: output enable configuration register (r/w, address = 12h) symbol position default description oe[7:0] oe.7-0 00h 0 = transmit drivers enabled. (default) 1 = transmit drivers in high-z.
36 IDT82V2048S octal t1/e1 short haul liu with sing le ended option industrial temperature ranges ais: alarm indication signal status register (r, address = 13h) symbol position default description ais[7:0] ais.7-0 00h 0 = normal operation. (default) 1 = ais detected. aism: alarm indication signal interrupt mask register (r/w, address = 14h) symbol position default description aism[7:0] aism.7-0 00h 0 = ais interrupt is not allowed. (default) 1 = ais interrupt is allowed. aisi: alarm indication signal interrupt st atus register (r, address = 15h) symbol position default description aisi[7:0] aisi.7-0 00h 0 = (default), or after an ais read operation 1 = any transition on aisn . (corresponding aismn is set to ?1?.) addp: address pointer control regi ster (r/w, address = 1f h) symbol position default description addp[7:0] addp.7-0 00h two kinds of configuration in this register can be set to sw itch between primary register bank and expanded register bank. when power up, the address pointer will point to the top address of primary register bank automatically. 00h = the address pointer points to the top address of primary register bank (default). aah = the address pointer points to the top address of expanded register bank.
37 IDT82V2048S octal t1/e1 short haul liu with sing le ended option industrial temperature ranges 3.2.2 expanded register description e-sing: single rail mode setting regi ster (r/w, expanded address = 00h) symbol position default description sing[7:0] sing.7-0 00h 0 = pin tdnn selects single rail mode or dual rail mode. (default) 1 = single rail mode enabled (with crsn=0) e-code: encoder/decoder selection regist er (r/w, expanded address = 01h) symbol position default description code[7:0] code.7-0 00h coden selects ami or b8zs/hdb3 encoder/decoder on a per channel basis with singn = 1 and crsn = 0. 0 = b8zs/hdb3 encoder/decoder enabled. (default) 1 = ami encoder/decoder enabled. e-crs: clock recovery enable/disable selecti on register (r/w, expanded address = 02h) symbol position default description crs[7:0] crs.7-0 00h 0 = clock recovery enabled. (default) 1 = clock recovery disabled. e-rpdn: receiver n powerdown register (r/w, expanded address = 03h) symbol position default description rpdn[7:0] rpdn.7-0 00h 0 = normal operation. (default) 1 = receiver n is powered down. e-tpdn: transmitter n powerdown register (r/w, expanded address = 04h) symbol position default description tpdn[7:0] tpdn.7-0 00h 0 = normal operation. (default) 1 = transmitter n is powered down (1) (the corresponding transmit output driver enters a low power high-z mode). 1. transmitter n is powered down w hen either pin tclkn is pulled low or tpdnn is set to ?1? e-czer: consecutive zero detect enable/disabl e register (r/w, expanded address = 05h) symbol position default description czer[7:0] czer.7-0 00h 0 = excessive zeros detect disabled. (default) 1 = excessive zeros detect enabled for b8zs/hdb3 decoder in single rail mode. e-codv: code violation detect enable/disable register (r/w, expanded address = 06h) symbol position default description codv[7:0] codv.7-0 00h 0 = code violation detect enable for b8zs/hdb3 decoder in single rail mode. (default) 1 = code violation detect disabled. e-srx: single ended receive termination enable/dis able register (r/w, expanded address = 07h) symbol position default description srx[7:0] srx.7-0 00h 0 = differential receive termination on rtipn and rringn (default). 1 = single ended receive termination on rtipn.
38 IDT82V2048S octal t1/e1 short haul liu with sing le ended option industrial temperature ranges e-lbcf: inband loopback configuration register (1) (r/w, expanded address = 08h) 1. this register is global control. symbol position default description -lbcf.7-600 0 = normal operation. (default) 1 = reserved. lbde lbcf.5 0 loopback detector enable 0 = inband loopback code detection is disabled. (default) 1 = inband loopback code detection is enabled. albe lbcf.4 0 automatic loopback enable 0 = automatic inband loopback disabled. 1 = automatic inband loopback enabled. lbal[1:0] lbcf.3-2 00 loopback activate code length 00 = 5-bit long activate code in lbac[7:3] is effective. 01 = 6-bit long activate code in lbac[7:2] is effective. 10 = 7-bit long activate code in lbac[7:1] is effective. 11 = 8-bit long activate code in lbac[7:0] is effective. lbdl[1:0] lbcf.1-0 00 loopback deactivate code length 00 = 5-bit long deactivate code in lbdc[7:3] is effective. 01 = 6-bit long deactivate code in lbdc[7:2] is effective. 10 = 7-bit long deactivate code in lbdc[7:1] is effective. 11 = 8-bit long deactivate code in lbdc[7:0] is effective. e-lbac: inband loopback activation code register (1)(2) (r/w, expanded address = 09h) 1. when setting a value in e-lbac or e-lbdc that is less than 8 bits, the most signi ficant bits must be replicated in the unused l east significant bits. e.g. if setting a 5-bit code = 11000, the register value should be 11000110. here b7 is repeated in b2; b6 is repeated in b1; b5 is repeated in b0. 2. this register is global control. symbol position default description lbac[7:0] lbac.7-0 00h lbac[7:0] = 8-bit (or 4-bit) repeating activate code is programmed with the length limitation in lbal[1:0]. lbac[7:1] = 7-bit repeating activate code is programmed with the length limitation in lbal[1:0]. lbac[7:2] = 6-bit (or 3-bit) repeating activate code is programmed with the length limitation in lbal[1:0]. lbac[7:3] = 5-bit repeating activate code is programmed with the length limitation in lbal[1:0]. e-lbdc: inband loopback deactivation code register (1)(2) (r/w, expanded address = 0ah) 1. when setting a value in e-lbac or e-lbdc that is less than 8 bi ts, the most significant bits must be replicated in the unused l east significant bits. e.g. if setting a 5-bit code = 11000, the register value should be 11000110. here b7 is repeated in b2; b6 is repeated in b1; b5 is repeated in b0. 2. this register is global control. symbol position default description lbdc[7:0] lbdc.7-0 00h lbdc[7:0] = 8-bit (or 4-bit) repeating deactivate code is programmed with the length limitation set by lbdl[1:0] bits. lbdc[7:1] = 7-bit repeating deactivate code is programmed with the length limitation set by lbdl[1:0] bits. lbdc[7:2] = 6-bit (or 3-bit) repeating deactivate code is programmed with the length limitation set by lbdl[1:0] bits. lbdc[7:3] = 5-bit repeating deactivate code is programmed with the length limitation set by lbdl[1:0] bits. e-lbs: inband loopback receive status register (r, expanded address = 0bh) symbol position default description lbs[7:0] lbs.7-0 00h 0 = normal operation (default). or loopback deactivation code detected. 1 = loopback activation code detected. e-lbm: inband loopback interrupt mask regi ster (r/w, expanded address = 0ch) symbol position default description lbm[7:0] lbm.7-0 00h 0 = lbi interrupt is not allowed (default) 1 = lbi interrupt is allowed.
39 IDT82V2048S octal t1/e1 short haul liu with sing le ended option industrial temperature ranges e-lbi: inband loopback interrupt status register (r, expanded address = 0dh) symbol position default description lbi[7:0] lbi.7-0 00h 0 = (default). or after a read of e-lbs operation. 1 = any transition on e-lbsn . (corresponding e-lbmn and bit lbde in e-lbcf are both set to 1.) e-lbgs: inband loopback activate/deactivate code generator selection register (r/w, expanded address = 0eh) symbol position default description lbgs[7:0] lbgs.7-0 00h 0 = activate code generator is selected in transmitter n. (default) 1 = deactivate code generator is selected in transmitter n. e-lbge: inband loopback activate/deactivate code generator enable register (r/w, expanded address = 0fh) symbol position default description lbge[7:0] lbge.7-0 00h 0 = activate/deactivate code generator for inband loopback is disabled in transmitter n. (default) 1 = activate/deactivate code generator for in band loopback is enabled in transmitter n.
40 IDT82V2048S octal t1/e1 short haul liu with sing le ended option industrial temperature ranges 4 ieee std 1149.1 jtag test access port the IDT82V2048S supports the digi tal boundary scan specification as described in the ieee 1149.1 standards. the boundary scan architecture cons ists of data and instruction registers plus a test access port (t ap) controller. control of the tap is achieved through signals applied to the tms and tck pins. data is shifted into the registers via the tdi pin, and shifted out of the registers via the tdo pin. jtag test data are clocked at a rate determined by jtag test clock. the jtag boundary scan registers includes bsr (boundary scan register), idr (device identification register), br (bypass register) and ir (instruction register). these will be described in the following pages. refer to figure-24 for architecture. 4.1 jtag instructions and instruction reg- ister (ir) the ir with instruction decode block is used to select the test to be executed or the data register to be accessed or both. the instructions are shifted in lsb first to this 3-bit register. see table-19 instruction register description on page 41 for details of the codes and the instructions related. figure-24 jtag architecture bsr (boundary scan register) idr (device identification register) br (bypass register) ir (instruction register) mux tdo tdi tck tms trst control<6:0> mux select high-z enable tap (test access port) controller parallel latched output digital output pins digital input pins
41 IDT82V2048S octal t1/e1 short haul liu with sing le ended option industrial temperature ranges 4.2 jtag data register 4.2.1 device identification register (idr) the idr can be set to define the producer number, part number and the device revision, which can be us ed to verify the proper version or revision number that has been used in the system under test. the idr is 32 bits long and is partitioned as in table-20 . data from the idr is shifted out to tdo lsb first. 4.2.2 bypass register (br) the br consists of a single bit. it can provide a serial path between the tdi input and tdo output, bypassi ng the bsr to reduce test access times. 4.2.3 boundary scan register (bsr) the bsr can apply and read test patterns in parallel to or from all the digital i/o pins. the bsr is a 98 bits long shift register and is initialized and read using the instruction extest or sample/preload. each pin is related to one or more bits in the bsr. please refer to table-21 for details of bsr bits and their functions. table-19 instruction register description ir code instruction comments 000 extest the external test instruction allows testing of the interconnection to other devices. when the current instruction is the extest instruction, the boundary scan register is placed between tdi and tdo. the signal on the input pins can be sampled by loading the boundary scan register using the captur e-dr state. the sampled values can then be viewed by shifting the boundary scan register using the shift-dr state. the signal on the output pins can be controlled by loading patterns shifted in through input tdi into the boundary scan register using the update-dr state. 100 sample/preload the sample instruction samples all the device inputs and outputs. for this instruction, the boundary scan register is placed between tdi and tdo. the normal path between IDT82V2048S logic and the i/o pins is maintained. primary device inputs and outputs can be sampled by loading the boundary scan register using the capture-dr state. the sampled val- ues can then be viewed by shifting the boundary scan register using the shift-dr state. 110 idcode the identification instruction is used to connect the identification register between tdi and tdo. the device's identifica- tion code can then be shifted out using the shift-dr state. 111 bypass the bypass instruction shifts data from input tdi to output tdo with one tck clock period delay. the instruction is used to bypass the device. table-20 device identification register description bit no. comments 0set to ?1? 1~11 producer number 12~27 part number 28~31 device revision table-21 boundary scan register description bit no. bit symbol pin signal type comments 0pout0lp0 i/o 1pin0lp0i/o 2pout1lp1 i/o 3pin1lp1i/o 4pout2lp2 i/o 5pin2lp2i/o 6pout3lp3 i/o 7pin3lp3i/o 8pout4lp4 i/o 9pin4lp4i/o 10 pout5 lp5 i/o 11 pin5 lp5 i/o 12 pout6 lp6 i/o 13 pin6 lp6 i/o 14 pout7 lp7 i/o 15 pin7 lp7 i/o
42 IDT82V2048S octal t1/e1 short haul liu with sing le ended option industrial temperature ranges 16 pios n/a - controls pins lp[7:0]. when ?0?, the pins are configured as outputs. the output values to the pins are set in pout 7~0. when ?1?, the pins are high-z. the input values to the pins are read in pin 7~0. 17 tclk1 tclk1 i 18 tdp1 tdp1 i 19 tdn1 tdn1 i 20 rclk1 rclk1 o 21 rdp1 rdp1 o 22 rdn1 rdn1 o 23 hzen1 n/a - controls pin rdp1, rdn1 and rclk1. when ?0?, the outputs are enabled on the pins. when ?1?, the pins are high-z. 24 los1 los1 o 25 tclk0 tclk0 i 26 tdp0 tdp0 i 27 tdn0 tdn0 i 28 rclk0 rclk0 o 29 rdp0 rdp0 o 30 rdn0 rdn0 o 31 hzen0 n/a - controls pin rdp0, rdn0 and rclk0. when ?0?, the outputs are enabled on the pins. when ?1?, the pins are high-z. 32 los0 los0 o 33 mode1 mode1 i 34 los3 los3 o 35 rdn3 rdn3 o 36 rdp3 rdp3 o 37 hzen3 n/a - controls pin rdp3, rdn3 and rclk3. when ?0?, the outputs are enabled on the pins. when ?1?, the pins are high-z. 38 rclk3 rclk3 o 39 tdn3 tdn3 i 40 tdp3 tdp3 i 41 tclk3 tclk3 i 42 los2 los2 o 43 rdn2 rdn2 o 44 rdp2 rdp2 o 45 hzen2 n/a - controls pin rdp2, rdn2 and rclk2. when ?0?, the outputs are enabled on the pins. when ?1?, the pins are high-z. 46 rclk2 rclk2 o 47 tdn2 tdn2 i 48 tdp2 tdp2 i 49 tclk2 tclk2 i 50 int int o 51 ack ack o 52 sdordys n/a - control pin ack . when ?0?, the output is enabled on pin ack . when ?1?, the pin is high-z. 53 wrb ds i 54 rdb r/ w i 55 ale ale i 56 csb cs i table-21 boundary scan regi ster description (continued) bit no. bit symbol pin signal type comments
43 IDT82V2048S octal t1/e1 short haul liu with sing le ended option industrial temperature ranges 57 mode0 mode0 i 58 tclk5 tclk5 i 59 tdp5 tdp5 i 60 tdn5 tdn5 i 61 rclk5 rclk5 o 62 rdp5 rdp5 o 63 rdn5 rdn5 o 64 hzen5 n/a - controls pin rdp5, rdn5 and rclk5. when ?0?, the outputs are enabled on the pins. when ?1?, the pins are high-z. 65 los5 los5 o 66 tclk4 tclk4 i 67 tdp4 tdp4 i 68 tdn4 tdn4 i 69 rclk4 rclk4 o 70 rdp4 rdp4 o 71 rdn4 rdn4 o 72 hzen4 n/a - controls pin rdp4, rdn4 and rclk4. when ?0?, the outputs are enabled on the pins. when ?1?, the pins are high-z. 73 los4 los4 o 74 oe oe i 75 clke clke i 76 los7 los7 o 77 rdn7 rdn7 o 78 rdp7 rdp7 o 79 hzen7 n/a - controls pin rdp7, rdn7 and rclk7. when ?0?, the outputs are enabled on the pins. when ?1?, the pins are high-z. 80 rclk7 rclk7 o 81 tdn7 tdn7 i 82 tdp7 tdp7 i 83 tclk7 tclk7 i 84 los6 los6 o 85 rdn6 rdn6 o 86 rdp6 rdp6 o 87 hzen6 n/a - controls pin rdp6, rdn6 and rclk6. when ?0?, the outputs are enabled on the pins. when ?1?, the pins are high-z. 88 rclk6 rclk6 o 89 tdn6 tdn6 i 90 tdp6 tdp6 i 91 tclk6 tclk6 i 92 mclk mclk i 93 mode2 mode2 i 94 a4 a4 i 95 a3 a3 i 96 a2 a2 i 97 a1 a1 i 98 a0 a0 i table-21 boundary scan regi ster description (continued) bit no. bit symbol pin signal type comments
44 IDT82V2048S octal t1/e1 short haul liu with sing le ended option industrial temperature ranges 4.3 test access po rt controller the tap controller is a 16-st ate synchronous state machine. figure- 25 shows its state diagram a descripti on of each state follows. note that the figure contains two main branc hes to access either the data or instruction registers. the value s hown next to each state transition in this figure states the value present at tms at each rising edge of tck. refer to table-22 for details of the state description. table-22 tap controller state description state description test logic reset in this state, the test logic is disabled. the device is set to normal operation. during initialization, the device initializes the instruction register with the idcode instruction. regardless of the original state of the controller, the controlle r enters the test-logic-reset state when the tms input is held high for at least 5 rising edges of tck. the controller remains in this state while tms is high. the device processor automatically enters this sta te at power-up. run-test/idle this is a controller state between scan operations. once in this state, the controller remains in the state as long as tms is h eld low. the instruction register and all test data registers retain their previous state. when tms is high and a rising edge is applied to tck, the controller moves to the select-dr state. select-dr-scan this is a temporary controller state and the instruction does not change in this state. the test data register selected by the current instruction retains its previous state. if tms is held low and a rising edge is applied to tck when in this state, the controller moves int o the capture-dr state and a scan sequence for the selected test data register is initiated. if tms is held high and a rising edge applied to tc k, the controller moves to the select-ir-scan state. capture-dr in this state, the boundary scan register captures input pin data if the current instruction is extest or sample/preload. the i nstruction does not change in this state. the other test data registers, which do not have parallel input, are not changed. when the tap c ontroller is in this state and a rising edge is applied to tck, the controller enters the exit1-dr state if tms is high or the shift-dr state i f tms is low. shift-dr in this controller state, the test data register connected between tdi and tdo as a result of the current instruction shifts da ta on stage toward its serial output on each rising edge of tck. the instruction does not change in this state. when the tap controller is in this state and a rising edge is applied to tck, the controller enters the exit1-dr state if tms is high or remains in the shift-dr state if tms is low. exit1-dr this is a temporary state. while in this state, if tms is held high, a rising edge applied to tck causes the controller to ente r the update-dr state, which terminates the scanning process. if tms is held low and a rising edge is applied to tck, the controller enters the pause-dr state. the test data register selected by the current instruction retains its previous value and the instruction does not chang e during this state. pause-dr the pause state allows the test controller to temporarily halt the shifting of data through the test data register in the seria l path between tdi and tdo. for example, this state could be used to allow the tester to reload its pin memory from disk during application of a l ong test sequence. the test data register selected by the current instruction retains its previous value and the instruction does not ch ange during this state. the controller remains in this state as long as tms is low. when tms goes high and a rising edge is applied to tck, the controller moves to the exit2-dr state. exit2-dr this is a temporary state. while in this state, if tms is held high, a rising edge applied to tck causes the controller to ente r the update-dr state, which terminates the scanning process. if tms is held low and a rising edge is applied to tck, the controller enters the shift-dr state. the test data register selected by the current instruction retains its previous value and the instruction does not change durin g this state. update-dr the boundary scan register is provided with a latched parallel output to prevent changes while data is shifted in response to t he extest and sample/preload instructions. when the tap controller is in this state and the boundary scan register is selected, data is l atched into the parallel output of this register from the shift-register path on the falling edge of tck. the data held at the latched para llel output changes only in this state. all shift-register stages in the test data register selected by the current instruction retain their previo us value and the instruc- tion does not change during this state. select-ir-scan this is a temporary controller state. the test data register selected by the current instruction retains its previous state. if tms is held low and a rising edge is applied to tck when in this state, the contro ller moves into the capture-ir state, and a scan sequence for the instruction reg- ister is initiated. if tms is held high and a rising edge is applied to tck, the controller moves to the test-logic-reset state . the instruction does not change during this state. capture-ir in this controller state, the shift register contained in the instruction register loads a fixed value of ?100? on the rising e dge of tck. this sup- ports fault-isolation of the board-level serial test data path. data registers selected by the current instruction retain their value and the instruc- tion does not change during this state. when the controller is in this state and a rising edge is applied to tck, the controlle r enters the exit1- ir state if tms is held high, or the shift-ir state if tms is held low. shift-ir in this state, the shift register contained in the instruction register is connected between tdi and tdo and shifts data one st age towards its serial output on each rising edge of tck. the test data register selected by the current instruction retains its previous value and the instruction does not change during this state. when the controller is in this state and a rising edge is applied to tck, the controller ent ers the exit1-ir state if tms is held high, or remains in the shift-ir state if tms is held low.
45 IDT82V2048S octal t1/e1 short haul liu with sing le ended option industrial temperature ranges figure-25 jtag state diagram exit1-ir this is a temporary state. while in this state, if tms is held high, a rising edge applied to tck causes the controller to ente r the update-ir state, which terminates the scanning process. if tms is held low and a rising edge is applied to tck, the controller enters the pause-ir state. the test data register selected by the current instruction retains its previous value and the instruction does not change durin g this state. pause-ir the pause state allows the test controller to temporarily halt the shifting of data through the instruction register. the test data register selected by the current instruction retains its previous value and the instruction does not change during this state. the controller rem ains in this state as long as tms is low. when tms goes high and a rising edge is applied to tck, the controller moves to the exit2-ir state. exit2-ir this is a temporary state. while in this state, if tms is held high, a rising edge applied to tck causes the controller to ente r the update-ir state, which terminates the scanning process. if tms is held low and a rising edge is applied to tck, the controller enters the shift-ir state. the test data register selected by the current instruction retains its previous value and the instruction does not change durin g this state. update-ir the instruction shifted into the instruction register is latched into the parallel output from the shift-register path on the f alling edge of tck. when the new instruction has been latched, it becomes the current instruction. the test data registers selected by the current instruction retain their previous value. table-22 tap controller stat e description (continued) state description test-logic reset run test/idle select-dr select-ir capture-dr capture-ir shift-dr shift-ir exit1-dr exit1-ir pause-dr pause-ir exit2-dr exit2-ir update-dr update-ir 1 0 0 1 1 1 00 00 0 0 1 1 1 0 1 0 1 1 1 0 1 0 1 0 1 1 0 0 0 1
46 IDT82V2048S octal t1/e1 short haul liu with sing le ended option industrial temperature ranges absolute maximum rating recommended operating conditions symbol parameter min max unit vdda, vddd core power supply -0.5 4.0 v vddio0, vddio1 i/o power supply -0.5 4.0 v vddt0-7 transmit power supply -0.5 7.0 v vin input voltage, any digital pin gnd-0.5 5.5 v input voltage (1) , rtipn pins and rringn pins 1. referenced to ground gnd-0.5 vdda+ 0.5 vddd+ 0.5 v v esd voltage, any pin (2) 2. human body model 2000 v iin transient latch-up current, any pin 100 ma input current, any digital pin (3) 3. constant input current -10 10 ma dc input current, any analog pin (3) 100 ma pd maximum power dissipation in package 1.6 w tc case temperature 120 c ts storage temperature -65 +150 c caution : exceeding these values may cause permanent damage. functional operation under these conditions is not implied. exposure to ab solute maximum rat- ing conditions for extended periods may affect device reliability. symbol parameter min typ max unit vdda, vddd core power supply 3.13 3.3 3.47 v vddio i/o power supply 3.13 3.3 3.47 v vddt (1) 1. for t1 applications, only 5v vddt is supported. transmitter supply 3.3 v 3.13 3.3 3.47 v 5 v 4.75 5.0 5.25 v t a ambient operating temperature -40 25 85 c r l output load at ttipn pins and tringn pins 25 ? i vdd average core power supply current (2) 2. maximum power and current consumption over the full operating temperature and power supply vo ltage range. includes all channels . 55 65 ma i vddio i/o power supply current (3) 3. digital output is driving 50 pf load, digita l input is within 10% of the supply rails. 15 25 ma i vddt average transmitter power supply current, t1 mode (2),(4),(5) 4. t1 maximum values measured with maximum c able length (len = 111). typical values meas ured with typical cable length (len = 101) . 5. power consumption includes power absorbed by line load and external transmitter components. 50% ones density data: 230 ma 100% ones density data: 440 ma
47 IDT82V2048S octal t1/e1 short haul liu with sing le ended option industrial temperature ranges power consumption dc characteristics symbol parameter len min typ max (1)(2) 1. maximum power and current consumption over the full operating temperature and power supply volt age range. includes all channels . 2. power consumption includes power absorbed by line load and external transmitter components. unit e1, 3.3 v, 75 ? load 50% ones density data: 100% ones density data: 000 000 - - 662 1100 - 1177 mw mw e1, 3.3 v, 120 ? load 50% ones density data: 100% ones density data: 000 000 - - 576 930 - 992 mw mw e1, 5.0 v, 75 ? load 50% ones density data: 100% ones density data: 000 000 - - 910 1585 - 1690 mw mw e1, 5.0 v, 120 ? load 50% ones density data: 100% ones density data: 000 000 - - 785 1315 - 1410 mw mw t1, 5.0 v, 100 ? load (3) 50% ones density data: 100% ones density data: 101 111 - - 1185 2395 - 2670 mw mw symbol parameter min typ max unit v il input low level voltage mode2, jas and lpn pins vddio-0.2 v all other digital inputs pins 0.8 v v im input mid level voltage mode2, jas and lpn pins vddio+0.2 vddio vddio-0.2 v v ih input high voltage mode2, jas and lpn pins vddio+ 0.2 v all other digital inputs pins 2.0 v v ol output low level voltage (1) (iout = 1.6 ma) 1. output drivers will output cmos logic levels into cmos loads. 0.4 v v oh output high level voltage (1) (iout = 400 a) 2.4 vddio v v ma analog input quiescent voltage (rtipn/rringn pin while floating) 1.33 1.4 1.47 v i h input high level current (mode2, jas and lpn pin) 50 a i l input low level current (mode2, jas and lpn pin) 50 a i i input leakage current tms, tdi and trst pins all other digital input pins -10 50 10 a a i zl high-z leakage current -10 10 a z oh output high-z on ttipn pins and tringn pins 150 k ? 1 3 --- 1 3 --- 1 2 --- 2 3 --- 2 3 ---
48 IDT82V2048S octal t1/e1 short haul liu with sing le ended option industrial temperature ranges transmitter characteristics symbol parameter min typ max unit v o-p output pulse amplitudes (1) e1, 75 ? load e1, 120 ? load t1, 100 ? load 1. e1: measured at the line output ports; t1: measured at the dsx 2.14 2.7 2.4 2.37 3.0 3.0 2.6 3.3 3.6 v v v v o-s zero (space) level e1, 75 ? load e1, 120 ? load t1, 100 ? load -0.237 -0.3 -0.15 0.237 0.3 0.15 v v v transmit amplitude variation with supply -1 +1 % difference between pulse sequences for 17 consecutive pulses 200 mv t pw output pulse width at 50% of nominal amplitude e1: t1: 232 338 244 350 256 362 ns ns ratio of the amplitudes of positive and negative pulses at the center of the pulse interval 0.95 1.05 rtx transmit return loss (2) 2. test at IDT82V2048S evaluation board e1, 75 ? 51 khz ? 102 khz 102 khz ? 2.048 mhz 2.048 mhz ? 3.072 mhz 15 15 15 db db db e1, 120 ? 51 khz ? 102 khz 102 khz ? 2.048 mhz 2.048 mhz ? 3.072 mhz 15 15 15 db db db t1 (vddt = 5 v) 51 khz ? 102 khz 102 khz ? 2.048 mhz 2.048 mhz ? 3.072 mhz 15 15 15 db db db jtx p-p intrinsic transmit jitter (tclk is jitter free, ja enabled) e1: 20 hz ? 100 khz 0.050 u.i. t1: 10 hz ? 8 khz 8 khz ? 40 khz 10 hz ? 40 khz wide band 0.020 0.025 0.025 0.050 u.i.p-p u.i.p-p u.i.p-p u.i.p-p td transmit path delay (ja is disabled) single rail dual rail 8 3 u.i. u.i. i sc line short circuit current (3) 3. measured on device, between ttipn and tringn 180 map
49 IDT82V2048S octal t1/e1 short haul liu with sing le ended option industrial temperature ranges receiver characteristics symbol parameter min typ max unit att permissible cable attenuation (e1: @ 1024 khz, t1: @ 772 khz) 14 db ia input amplitude differential interface single ended interface 0.9 1.3 vp vp sir signal to interference ratio margin (1) 1. e1: per g.703, o.151 @ 6 db cable attenuation. t1: @ 655 ft. of 22 abam cable -14 db sre data decision threshold (refer to peak input voltage) 50 % data slicer threshold 150 mv analog loss of signal (2) declare/clear (differential interface): declare/clear (single ended interface): 2. measured on device, between rtip and rring, all ones signal. 120/150 95/118 200/250 158/197 280/350 221/276 mvp mvp allowable consecutive zeros before los e1, g.775: e1, etsi 300 233: t1, t1.231-1993 32 2048 175 los reset clock recovery mode 12.5 % ones jrx p-p peak to peak intrinsic receive jitter (ja disabled) e1 (wide band): t1 (wide band): 0.0625 0.0625 u.i. u.i. jtrx jitter tolerance e1: 1 hz ? 20 hz 20 hz ? 2.4 khz 18 khz ? 100 khz 18.0 1.5 0.2 u.i. u.i. u.i. t1: 0.1 hz ? 1 hz 4.9 hz ? 300 hz 10 khz ? 100 khz 138.0 28.0 0.4 u.i. u.i. u.i. zdm receiver differential input impedance 120 k ? zcm receiver common mode input impedance to gnd 10 k ? rrx receive return loss 51 khz ? 102 khz 102 khz ? 2.048 mhz 2.048 mhz ? 3.072 mhz 20 20 20 db db db receive path delay dual rail single rail 3 8 u.i. u.i.
50 IDT82V2048S octal t1/e1 short haul liu with sing le ended option industrial temperature ranges jitter attenuator characteristics symbol parameter min typ max unit f -3db jitter transfer function corner frequency (?3 db) host mode e1, 32/64 bit fifo jabw = 0: jabw = 1: t1, 32/64 bit fifo jabw = 0: jabw = 1: 1.7 6.6 2.5 5 hz hz hz hz hardware mode e1 t1 1.7 2.5 hz hz jitter attenuator e1 (1) : @ 3 hz @ 40 hz @ 400 hz @ 100 khz 1. per g.736, see figure-42 on page 61 . -0.5 -0.5 +19.5 +19.5 db db db db t1 (2) : @ 1 hz @ 20 hz @ 1 khz @ 1.4 khz @ 70 khz 2. per at&t pub.62411, see figure-43 on page 61 . 0 0 +33.3 40 40 db db db db db td jitter attenuator latency delay 32 bit fifo: 64 bit fifo: 16 32 u.i. u.i. input jitter tolerance before fifo overflow or underflow 32 bit fifo: 64 bit fifo: 28 56 u.i. u.i. output jitter in remote loopback (3) 3. per etsi ctr12/13 output jitter. 0.11 u.i.
51 IDT82V2048S octal t1/e1 short haul liu with sing le ended option industrial temperature ranges transceiver timing characteristics symbol parameter min typ max unit mclk frequency e1: t1: 2.048 1.544 mhz mhz mclk tolerance -100 100 ppm mclk duty cycle 40 60 % transmit path tclk frequency e1: t1: 2.048 1.544 mhz mhz tclk tolerance -50 +50 ppm tclk duty cycle 10 90 % t1 transmit data setup time 40 ns t2 transmit data hold time 40 ns delay time of oe low to driver high-z 1s delay time of tclk low to driver high-z 40 44 48 s receive path clock recovery capture range (1) 1. relative to nominal frequency, mclk = 100 ppm e1: 80 ppm t1: 180 ppm rclk duty cycle (2) 2. rclk duty cycle widths will vary depending on extent of received pulse jitter displacement. maximum and minimum rclk duty cycle s are for worst case jitter conditions (0.2 ui dis- placement for e1 per itu g.823). 40 50 60 % t4 rclk pulse width (2) e1: t1: 457 607 488 648 519 689 ns ns t5 rclk pulse width low time e1: t1: 203 259 244 324 285 389 ns ns t6 rclk pulse width high time e1: t1: 203 259 244 324 285 389 ns ns rise/fall time (3) 3. for all digital outputs. c load = 15 pf 530ns t7 receive data setup time e1: t1: 200 200 244 324 ns ns t8 receive data hold time e1: t1: 200 200 244 324 ns ns t9 rdpn/rdnn pulse width (mclk = high) (4) 4. clock recovery is disabled in this mode. e1: t1: 200 300 244 324 ns ns
52 IDT82V2048S octal t1/e1 short haul liu with sing le ended option industrial temperature ranges figure-26 transmit system interface timing figure-27 receive system interface timing bpvin/tdnn tdn/tdpn tclkn t1 t2 cvn/rdnn rdn/rdpn rclkn t4 t7 t6 t7 t5 t8 t8 (clke = 0) (clke = 1) rdn/rdpn cvn/rdnn
53 IDT82V2048S octal t1/e1 short haul liu with sing le ended option industrial temperature ranges jtag timing characteristics figure-28 jtag interface timing symbol parameter min typ max unit comments t1 tck period 200 ns t2 tms to tck setup time tdi to tck setup time 50 ns t3 tck to tms hold time tck to tdi hold time 50 ns t4 tck to tdo delay time 100 ns tck t1 t2 t3 tdo tms tdi t4
54 IDT82V2048S octal t1/e1 short haul liu with sing le ended option industrial temperature ranges parallel host interface timing characteristics intel mode read timing characteristics symbol parameter min typ max unit comments t1 active rd pulse width 90 ns (1) 1. the t1 is determined by the start time of the valid data when the rdy signal is not used. t2 active cs to active rd setup time 0 ns t3 inactive rd to inactive cs hold time 0 ns t4 valid address to inactive ale setup time (in multiplexed mode) 5 ns t5 invalid rd to address hold time (in non-multiplexed mode) 0 ns t6 active rd to data output enable time 7.5 15 ns t7 inactive rd to data high-z delay time 7.5 15 ns t8 active cs to rdy delay time 6 12 ns t9 inactive cs to rdy high-z delay time 6 12 ns t10 inactive rd to inactive int delay time 20 ns t11 address latch enable pulse width (in multiplexed mode) 10 ns t12 address latch enable to rd setup time (in multiplexed mode) 0 ns t13 address setup time to valid data time (in non-multiplexed mode) 18 32 ns t14 inactive rd to active rdy delay time 10 15 ns t15 active rd to active rdy delay time 30 85 ns t16 inactive ale to address hold time (in multiplexed mode) 5 ns
55 IDT82V2048S octal t1/e1 short haul liu with sing le ended option industrial temperature ranges figure-29 non-multiplexed intel mode read timing figure-30 multiplexed intel mode read timing int rdy d[7:0] a[4:0] ale(=1) rd cs t1 t2 t3 t5 t6 t7 t8 t9 t10 t13 address data out t14 t15 int rdy ad[7:0] ale rd cs t1 t2 t3 t6 t7 t8 t9 t10 t4 t11 t12 address data out t15 t14 t16 t13
56 IDT82V2048S octal t1/e1 short haul liu with sing le ended option industrial temperature ranges intel mode write timing characteristics figure-31 non-multiplexe d intel mode write timing figure-32 multiplexed intel mode write timing symbol parameter min typ max unit comments t1 active wr pulse width 90 ns (1) 1. the t1 can be 15 ns when rdy signal is not used. t2 active cs to active wr setup time 0 ns t3 inactive wr to inactive cs hold time 0 ns t4 valid address to latch enable setup time (in multiplexed mode) 5 ns t5 invalid wr to address hold time (in non-multiplexed mode) 2 ns t6 valid data to inactive wr setup time 5 ns t7 inactive wr to data hold time 10 ns t8 active cs to inactive rdy delay time 6 12 ns t9 active wr to active rdy delay time 30 85 ns t10 inactive wr to inactive rdy delay time 10 15 ns t11 invalid cs to rdy high-z delay time 6 12 ns t12 address latch enable pulse width (in multiplexed mode) 10 ns t13 inactive ale to wr setup time (in multiplexed mode) 0 ns t14 inactive ale to address hold time (in multiplexed mode) 5 ns t15 address setup time to inactive wr time (in non-multiplexed mode) 5 ns rdy d[7:0] a[4:0] ale(=1) wr cs t2 t1 t3 t5 t6 t7 t8 t9 t10 t11 address write data t15 rdy ad[7:0] ale wr cs t1 t2 t3 t6 t7 t8 t9 t10 t4 t12 t13 write data address t11 t14
57 IDT82V2048S octal t1/e1 short haul liu with sing le ended option industrial temperature ranges motorola mode read timing characteristics figure-33 non-multiplexed motorola mode read timing figure-34 multiplexed motorola mode read timing symbol parameter min typ max unit comments t1 active ds pulse width 90 ns (1) 1. the t1 is determined by the start time of the valid data when the ack signal is not used. t2 active cs to active ds setup time 0 ns t3 inactive ds to inactive cs hold time 0 ns t4 valid r/ w to active ds setup time 0 ns t5 inactive ds to r/ w hold time 0.5 ns t6 valid address to active ds setup time (in non-multiplexed mode) 5 ns t7 active ds to address hold time (in non-multiplexed mode) 10 ns t8 active ds to data valid delay time (in non-multiplexed mode) 20 35 ns t9 active ds to data output enable time 7.5 15 ns t10 inactive ds to data high-z delay time 7.5 15 ns t11 active ds to active ack delay time 30 85 ns t12 inactive ds to inactive ack delay time 10 15 ns t13 inactive ds to invalid int delay time 20 ns t14 active as to active ds setup time (in multiplexed mode) 5 ns int ack d[7:0] a[4:0] ale(=1) ds cs t1 address data out r/ w t2 t3 t4 t5 t6 t8 t10 t11 t12 t13 t7 t9 int ack ad[7:0] as ds cs data out address r/ w t1 t2 t3 t4 t5 t6 t7 t8 t11 t10 t12 t13 t14 t9
58 IDT82V2048S octal t1/e1 short haul liu with sing le ended option industrial temperature ranges motorola mode write timing characteristics figure-35 non-multiplexed motorola mode write timing figure-36 multiplexed mo torola mode writing timing symbol parameter min typ max unit comments t1 active ds pulse width 90 ns (1) 1. the t1 can be 15ns when the ack signal is not used. t2 active cs to active ds setup time 0 ns t3 inactive ds to inactive cs hold time 0 ns t4 valid r/ w to active ds setup time 10 ns t5 inactive ds to r/ w hold time 0 ns t6 valid address to active ds setup time (in non-multiplexed mode) 10 ns t7 valid ds to address hold time (in non-multiplexed mode) 10 ns t8 valid data to inactive ds setup time 5 ns t9 inactive ds to data hold time 10 ns t10 active ds to active ack delay time 30 85 ns t11 inactive ds to inactive ack delay time 10 15 ns t12 active as to active ds (in multiplexed mode) 0 ns t13 inactive ds to inactive as hold time (in multiplexed mode) 15 ns ack d[7:0] a[4:0] ale(=1) ds cs t1 address write data r/ w t2 t3 t4 t6 t7 t5 t8 t9 t10 t11 ack ad[7:0] as ds cs write data address r/ w t1 t2 t3 t4 t5 t6 t7 t8 t9 t13 t10 t11 t12
59 IDT82V2048S octal t1/e1 short haul liu with sing le ended option industrial temperature ranges serial host interface timing characteristics figure-37 serial interface write timing figure-38 serial interface read timing with clke = 0 figure-39 serial interface read timing with clke = 1 symbol parameter min typ max unit comments t1 sclk high time 25 ns t2 sclk low time 25 ns t3 active cs to sclk setup time 10 ns t4 last sclk hold time to inactive cs time 50 ns t5 cs idle time 50 ns t6 sdi to sclk setup time 5 ns t7 sclk to sdi hold time 5 ns t8 rise/fall time (any pin) 100 ns t9 sclk rise and fall time 50 ns t10 sclk to sdo valid delay time 25 35 ns load = 50 pf t11 sclk falling edge to sdo high-z hold time (clke = 0) or cs rising edge to sdo high-z hold time (clke = 1) 100 ns msb lsb lsb cs sclk sdi t1 t2 t3 t4 t5 t6 t7 t7 control byte data byte 12345678910111213141516 7 6 5 4 3 2 1 0 sdo cs sclk t4 t11 t10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 7 6 5 4 3 2 1 0 sdo cs sclk t4 t11 t10
60 IDT82V2048S octal t1/e1 short haul liu with sing le ended option industrial temperature ranges jitter tolerance performance e1 jitter tolerance performance figure-40 e1 jitter tolerance performance t1 jitter tolerance performance figure-41 t1 jitter tolerance performance g.823 IDT82V2048S 1 10 100 1 10 3 1 10 4 1 10 5 0.1 1 10 100 1 10 3 18 ui @ 1.8 hz 1.5 ui @ 20 hz 1.5 ui @ 2.4 khz 0.2 ui @ 18 khz frequency (hz) jitter (ui) test condition: prbs 2^15-1; line code rule hdb3 is used. at&t62411 IDT82V2048S 1 10 100 1 10 3 1 10 4 1 10 5 0.1 1 10 100 1 10 3 28 ui @ 4.9 hz 28 ui @ 300 hz 0.4 ui @ 10khz frequency (hz) jitter (ui) test condition: qrss; li ne code rule b8zs is used.
61 IDT82V2048S octal t1/e1 short haul liu with sing le ended option industrial temperature ranges jitter transfer performance e1 jitter transfer performance figure-42 e1 jitter transfer performance t1 jitter transfer performance figure-43 t1 jitter transfer performance g.736 1 10 100 1 10 3 1 10 4 1 10 5 -60 -40 -20 0 IDT82V2048S 0.5 db @ 3 hz 0.5 db @ 40 hz -19.5 db @ 400 hz -19.5 db @ 20 khz f 3db = 6.5 hz f 3db = 1.7 hz frequency (hz) gain (db) test condition: prbs 2^15-1; line code rule hdb3 is used. 1 10 100 1 10 3 1 10 4 1 10 5 -60 -40 -20 0 at&t62411 gr-253-core tr-tsy-000009 IDT82V2048S 0 db @ 1 hz -6 db @ 2 hz 0 db @ 20 hz 0.1 db @ 40 hz 0.5 db @ 350 hz -60 db @ 57 hz f 3db = 2.5 hz f 3db = 5 hz -33.3 db @ 1 khz -40 db @ 1.4 khz -40 db @ 70 khz -33.7 db @ 2.5 khz -49.2 db @ 15 khz frequency (hz) gain (db) test condition: qrss; line code rule b8zs is used.
IDT82V2048S octal t1/e1 short haul liu with sing le ended option industrial temperature ranges idt and the idt logo are trademarks of integrated device technology, inc. 62 corporate headquarters 6024 silver creek valley road san jose, ca 95138 www.idt.com for sales: 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 for tech support: 408-360-1552 email:telecomhelp@idt.com ordering information idt xxxxxxx xx x device type blank process/ temperature range bb 82v2048s industrial (-40 c to + 85 c) plastic ball grid array (pbga, bb160) t1/e1 short haul liu with single ended option da thin quad flatpack (tqfp, da144) bbg green plastic ball grid array (pbga, bbg160) dag green thin quad flatpack (tqfp, dag144) package

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